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...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
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| Number | Title | Issue Date |
| 8130014 | Network and method for setting a time-base of a node in the network A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to the master clocks. The synchronization system may, for determine a time... | 03/06/2012 |
| 8125251 | Semiconductor memory device having a clock alignment training circuit and method for operating the same A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by d... | 02/28/2012 |
| 8115524 | Semiconductor device having auto clock alignment training mode circuit A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment t... | 02/14/2012 |
| 8035429 | Semiconductor device and driving method thereof A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission pa... | 10/11/2011 |
| 7924071 | Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method Provided is a synchronization detection circuit including: a multiphase clock generation circuit which includes a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which g... | 04/12/2011 |
| 7852131 | Receiver circuit of semiconductor memory apparatus A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and contr... | 12/14/2010 |
| 7791383 | Semiconductor device having input circuits activated by clocks having different phases Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD... | 09/07/2010 |
| 7777538 | Method and apparatus for slew rate control Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the dat... | 08/17/2010 |
| 7768325 | Circuit and design structure for synchronizing multiple digital signals Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical ... | 08/03/2010 |
| 7751274 | Extended synchronized clock Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with th... | 07/06/2010 |
| 7692457 | Dual-path clocking architecture A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL ... | 04/06/2010 |
| 7659759 | Phase synchronous circuit An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. F... | 02/09/2010 |
| 7622965 | Dual-edge shaping latch/synchronizer for re-aligning edges Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal, ... | 11/24/2009 |
| 7616034 | Circuit for controlling data output Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection... | 11/10/2009 |
| 7521973 | Clock-skew tuning apparatus and method A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a... | 04/21/2009 |
| 7428169 | Nonvolatile semiconductor memory device and voltage generating circuit for the same A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage ge... | 09/23/2008 |
| 7424046 | Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe... | 09/09/2008 |
| 7423461 | Phase synchronous circuit An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. F... | 09/09/2008 |
| 7400180 | Semiconductor device having input circuits activated by clocks having different phases Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD... | 07/15/2008 |
| 7397880 | Synchronization circuit and synchronization method In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the ph... | 07/08/2008 |
| 7391841 | Frequency synthesizer A plurality of voltage controlled oscillators and a plurality of dividers are provided corresponding to a plurality of frequency bands, respectively, and a phase comparator, a charge pump, and a low pass filter are used in common for the plurality of frequency bands... | 06/24/2008 |
| 7375553 | Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elemen... | 05/20/2008 |
| 7375561 | Timing adjustment circuit and method thereof A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a f... | 05/20/2008 |
| 7373569 | Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also com... | 05/13/2008 |
| 7363563 | Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transm... | 04/22/2008 |
| 7355462 | Phase lock loop and method for operating the same A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital... | 04/08/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7352816 | Data oversampling via clock and data interpolation An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second ... | 04/01/2008 |
| 7352836 | System and method of cross-clock domain rate matching Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock... | 04/01/2008 |
| 7342565 | Display device and a driver circuit thereof To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inver... | 03/11/2008 |
| 7340629 | Method and system for application-based normalization of processor clocks in a multiprocessor environment A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first processor is obtained such that the first processor executes one or mor... | 03/04/2008 |
| 7340631 | Drift-tolerant sync pulse circuit in a sync pulse generator A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock do... | 03/04/2008 |
| 7333516 | Interface for synchronous data transfer between domains clocked at different frequencies The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is select... | 02/19/2008 |
| 7330488 | System, method, and article of manufacture for synchronizing time of day clocks on first and second computers A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, r... | 02/12/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7319349 | Semiconductor integrated circuit A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are sy... | 01/15/2008 |
| 7310397 | Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock p... | 12/18/2007 |
| 7305058 | Multi-standard clock rate matching circuitry Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control ... | 12/04/2007 |
| 7301375 | Off-chip driver circuit and data output circuit using the same An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip... | 11/27/2007 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
