Class 327/141 - Synchronizing

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein a signal is produced which will (a)
No. of patents: 1047
Last issue date: 03/13/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8134391	Semiconductor devices with signal synchronization circuits Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus includes an independent synchronization circuit and a dependent synchroniz...	03/13/2012
8030977	Clock generating circuit A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at ...	10/04/2011
8013644	Power supply circuit for south bridge chip A power supply circuit for a south bridge chip includes a voltage sampling circuit, a control circuit, and an I/O controller. The voltage sampling circuit comprises an input terminal capable of receiving a first voltage, and an output terminal capable of outputting ...	09/06/2011
7965111	Method and apparatus for divider unit synchronization A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a ...	06/21/2011
7863949	Circuit and design structure for synchronizing multiple digital signals Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical ...	01/04/2011
7791381	Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a clock tree circuit for delay-adjusting a clock signal using various delay amounts, and a clock synchronizing circuit to which the delay-adjusted clock signal is supplied. The clock tre...	09/07/2010
7791382	Semiconductor integrated circuit Provided is a semiconductor integrated circuit which includes a logical operation circuit, a clock generator, a relay circuit, and a signal generating unit that are integrated. The clock generator generates multiphase clocks. The relay circuit distributes the genera...	09/07/2010
7777536	Synchronization circuit A synchronization circuit includes a first flip-flop circuit to hold an input signal which is asynchronous to a clock signal by the clock signal, and output an output signal, a second flip-flop circuit to hold the input signal by a signal of an opposite phase to the...	08/17/2010
7737740	Integrated circuit with a programmable delay and a method thereof An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block havin...	06/15/2010
RE41337	Synchronous test mode initialization The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal...	05/18/2010
7659757	Glitch-free clock regeneration circuit A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being ...	02/09/2010
7629818	Method for checking the integrity of a clock tree A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result...	12/08/2009
7619449	Method and apparatus for synchronous clock distribution to a plurality of destinations Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a d...	11/17/2009
7616030	Semiconductor device and operation method thereof Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock an...	11/10/2009
7443938	Method and system for synchronization between transmitter and receiver in a communication system A method and system for synchronization between a transmitter and a receiver in a communication system is provided. The receiver receives a plurality of signals from the transmitter. According to this method, a frequency burst is detected in the received signal at t...	10/28/2008
7443217	Circuit and method to balance delays through true and complement phases of differential and complementary drivers A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay dev...	10/28/2008
7439773	Integrated circuit communication techniques An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which d...	10/21/2008
7436919	Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles o...	10/14/2008
7436904	Data recovery apparatus and method for decreasing data recovery error in a high-speed serial link Provided are a data recovery apparatus and method for recovering (parallel) data from serial data received via a high-speed serial link with a reduced data recovery error rate. The data recovery apparatus includes a clock signal generating circuit and a data recover...	10/14/2008
7436906	Synchronous detector with high accuracy in detecting synchronization and a method therefor In a symbol timing detector, a correlator calculates a correlation value for a received radio packet signal. A peak detector compares the correlation value with a threshold value to be used, and sends, upon a correlation value detected larger than the threshold valu...	10/14/2008
7433392	Wireless communications device performing block equalization based upon prior, current and/or future autocorrelation matrix estimates and related methods A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective ch...	10/07/2008
7433430	Wireless communications device providing enhanced block equalization and related methods A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generatin...	10/07/2008
7430259	Two-wire chip-to-chip interface A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for transmission over the serial interface between a master device and a...	09/30/2008
7430680	System and method to align clock signals A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers...	09/30/2008
7427885	Semiconductor device having a power supply capacitor In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals;...	09/23/2008
7424046	Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe...	09/09/2008
7421048	System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ...	09/02/2008
7421606	DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x ...	09/02/2008
7421607	Method and apparatus for providing symmetrical output data for a double data rate DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, arr...	09/02/2008
7403447	Method for stabilizing electronic circuit operation and electronic apparatus using the same An operation signal generator circuits are provided to continue to operate an object circuit which is not operated unless an operation signal arrives for the purpose of power consumption reduction, and thereby the object circuit is put into dummy operation. This ena...	07/22/2008
7398412	Measure controlled delay with duty cycle control The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a dela...	07/08/2008
7391255	Semiconductor phase adjustment system module A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in...	06/24/2008
7382844	Methods to self-synchronize clocks on multiple chips in a system A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip,...	06/03/2008
7382678	Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de...	06/03/2008
7375560	Method and apparatus for timing domain crossing A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which ...	05/20/2008
7376190	Asynchronous data transmitting apparatus An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits...	05/20/2008
7375553	Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elemen...	05/20/2008
7373560	Circuit for measuring signal delays of asynchronous inputs of synchronous elements A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during measurement operations. The delay between one of the test circuit's asy...	05/13/2008
7373575	Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ...	05/13/2008
7369634	Training pattern for a biased clock recovery tracking loop Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alig...	05/06/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Class 327/141 - Synchronizing