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| Number | Title | Issue Date |
| 8081019 | Variable PFC and grid-tied bus voltage control An apparatus for generating a compensation signal for a power converter where the second harmonic ripple on the voltage bus is substantially removed from the compensation signal. The apparatus comprises a frequency-locked clock generator, a bus voltage data generato... | 12/20/2011 |
| 7683683 | Frequency doubler with duty-cycle correction and associated methods An apparatus includes a controllable delay circuit, a clock doubler circuit, a low-pass filter, and a comparator. The controllable delay circuit generates a delayed clock signal from a reference clock signal. The clock doubler circuit generates an output clock signa... | 03/23/2010 |
| 7579884 | Frequency doubler device A frequency doubler circuit includes first and second arrangements of switches connected to the positive and negative inputs of a comparator, respectively, and arranged in such a way that first and third voltages during the first phase of a reference clock signal an... | 08/25/2009 |
| 7375599 | Analog circuit and method for multiplying clock frequency A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator an... | 05/20/2008 |
| 7356318 | Quadrature subharmonic mixer A quadrature subharmonic mixer comprises a polyphase filter configured to generate quadrature components of a local oscillator (LO) reference signal, a summing and scaling element configured to create additional components of the LO reference signal, and a plurality... | 04/08/2008 |
| 7332970 | Integrated amplifier, electronic communication unit with integrated amplifier and method for operating the electronic communication unit with an integrated amplifier An integrated amplifier has a resonant circuit with a tuneable center frequency, in which the resonant circuit has at least one coil and at least one varactor for varying a resonant frequency of the resonant circuit. ... | 02/19/2008 |
| 7332964 | Gain-step transconductor A gain-step transconductor circuit operates with multiple gain values. The gain can be stepped from one gain value to another by selecting a different signal path between an input node and an output amplifier. The output amplifier may operate as a common source ampl... | 02/19/2008 |
| 7312660 | Differential amplifier and active load for the same The differential amplifier and an active load are provided. The differential amplifier includes a differential input section which is configured to generate a differential current according to a differential input signal; and an active load which is configured to ge... | 12/25/2007 |
| 7302011 | Quadrature frequency doubling system The frequency doubler of the present invention operates to provide an in-phase signal and a quadrature signal, each having a frequency equal to twice the frequency of a reference signal. The in-phase and quadrature signals are based on signals that are 0 degrees, 45... | 11/27/2007 |
| 7295048 | Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of... | 11/13/2007 |
| 7277499 | Additive DC component detection included in an input burst signal A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detect... | 10/02/2007 |
| 7271631 | Clock multiplication circuit A clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The circuit delivers an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as i... | 09/18/2007 |
| 7271647 | Active polyphase filter The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first res... | 09/18/2007 |
| 7265581 | Level shifter The level shifter comprises a coupling block, a PMOS switch, a first PMOS transistor and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and t... | 09/04/2007 |
| 7254208 | Delay line based multiple frequency generator circuits for CDMA processing A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay lin... | 08/07/2007 |
| 7245164 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 07/17/2007 |
| 7239854 | Frequency-doubling circuit arrangement, and mobile radio having that circuit arrangement One or more aspects of the present invention are directed to a frequency-doubling circuit arrangement that doubles the frequency of a signal applied to its input, and presents that doubled frequency signal at its output. A rectifier that rectifies the input signal a... | 07/03/2007 |
| 7236058 | Low frequency doubler A circuit and corresponding method for doubling the frequency of an input signal, even when the input signal is of low frequency or a square wave. The input signal is applied to a phase-shifting circuit that produces a pair of output signals that are theoretically 9... | 06/26/2007 |
| 7230488 | Amplifying circuit, noise reducing apparatus and power converting apparatus An amplifying circuit, which generates a compensation current based on a detection result of a leakage current flowing between an AC power source for supplying power and a power converting circuit section, includes a main amplifier having transistors and a correctio... | 06/12/2007 |
| 7227809 | Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a first output clock signal that is synchronized with a first input clock signal and adjusts a second adjusta... | 06/05/2007 |
| 7227392 | Frequency multiplier A multiplier core outputs a single-phase signal containing a frequency component having a frequency which is an even multiple of the frequency of an input signal. A differential amplifier includes first and second nMOS transistors having respective source terminals ... | 06/05/2007 |
| 7218156 | Supply tracking clock multiplier A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power con... | 05/15/2007 |
| 7180342 | Frequency doubler circuit with trimmable current control A frequency doubler circuit with trimmable current control. In one embodiment, the present invention provides a circuit comprising an oscillator with a current source and a frequency doubler circuit coupled to the current source. In one embodiment, the current sourc... | 02/20/2007 |
| 7133484 | High-frequency clock generator with low power consumption A high-frequency clock generator with low power consumption is made up of a single phase-locked loop and a serially-connected sampling circuit coupled thereto. The phase-locked loop includes a voltage-controlled oscillator which is configured to provide multiple low... | 11/07/2006 |
| 7132863 | Digital clock frequency doubler A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock si... | 11/07/2006 |
| 7132873 | Method and apparatus for avoiding gated diode breakdown in transistor circuits An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high ... | 11/07/2006 |
| 7119588 | Circuit for multiplying continuously varying signals A means for obtaining an output signal which is the sum of the frequencies of two periodic input signals that may vary in amplitude and frequency over time. The apparatus, which provides means for realizing trigonometric functions of the form sin(α+β)=2 sin α cos... | 10/10/2006 |
| 7116141 | Frequency-doubling delay locked loop A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs ... | 10/03/2006 |
| 7091757 | Frequency generator and communication system The object of the invention is to provide a frequency generator which is composed of an oscillator and a frequency doubler and in which difference in amplitude between differential outputs of the frequency doubler can be equalized at low power consumption without ad... | 08/15/2006 |
| 7075346 | Synchronized frequency multiplier for multiple phase PWM control switching regulator without using a phase locked loop A method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A period of the input clock signal is measured by... | 07/11/2006 |
| 7061285 | Clock doubler A clock doubler including clock doubling circuitry for generating from a system clock a clock signal having a frequency substantially double that of the system clock and also having a pulse width and associated duty cycle is provided. Timing circuitry for generating... | 06/13/2006 |
| 7053721 | Oscillator having a resonant circuit and a drive circuit An oscillator includes a resonant circuit generating a resonant signal, a drive circuit that feeds back the resonant signal to the resonant circuit, and an output terminal connected to a given node of the resonant circuit, an oscillation signal of the oscillator bei... | 05/30/2006 |
| 7053682 | Device and method for clock generation A clock generator includes an interface for receiving a plurality of n periodical signals of the same frequency which are phase-shifted with respect to each other, wherein n/3. Further, a clock signal generator is provided for generating respective clock edges of a ... | 05/30/2006 |
| 7031372 | Multiple user reconfigurable CDMA processor A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and genera... | 04/18/2006 |
| 7020450 | Active inductors using bipolar silicon transistors An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and betw... | 03/28/2006 |
| 7019565 | Methods and systems for fully differential frequency doubling Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or ne... | 03/28/2006 |
| 7005900 | Counter-based clock doubler circuits and methods with optional duty cycle correction and offset Clock doubler circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the count... | 02/28/2006 |
| 6980041 | Non-iterative introduction of phase delay into signal without feedback Non-iterative introduction of phase delay into a signal, without feedback, is disclosed. A system of one embodiment of the invention includes a controller and a mechanism. The controller provides a pulse having a length representative of a phase delay for introducti... | 12/27/2005 |
| 6967508 | Compact frequency doubler/multiplier circuitry The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and s... | 11/22/2005 |
| 6944099 | Precise time period measurement Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit ... | 09/13/2005 |
