...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 8179163 | Method and apparatus for charge pump linearization in fractional-PLLs Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinea... | 05/15/2012 |
| 8138800 | Phase detecting circuit and PLL circuit A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase sid... | 03/20/2012 |
| 8026742 | Phase detector In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal suppl... | 09/27/2011 |
| 8008947 | Balanced phase detector Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the p... | 08/30/2011 |
| 7965108 | Frequency synthesizer A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divid... | 06/21/2011 |
| 7940088 | High speed phase frequency detector Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circ... | 05/10/2011 |
| 7919992 | Charge recycling amplifier for a high dynamic range CMOS imager A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplificat... | 04/05/2011 |
| 7893725 | Delay locked loop circuit The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detect... | 02/22/2011 |
| 7893724 | Method and circuit for rapid alignment of signals Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of ... | 02/22/2011 |
| 7839178 | High speed digital phase/frequency comparator for phase locked loops An apparatus and method for detecting a phase difference between an input signal and a reference signal in an all-digital phase locked loop (PLL) are provided. In a preferred embodiment, an N-stage tapped delay line and N-bit parallel latch are used to create a snap... | 11/23/2010 |
| 7839179 | Balanced phase detector Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the p... | 11/23/2010 |
| 7821301 | Method and apparatus for measuring and compensating for static phase error in phase locked loops A method and circuit for static phase error measurement includes a reference clock delay chain having a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a reference clock signal. A fee... | 10/26/2010 |
| 7791378 | Phase detector In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal suppl... | 09/07/2010 |
| 7755397 | Methods and apparatus for digital phase detection with improved frequency locking Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and t... | 07/13/2010 |
| 7750683 | Phase/frequency detector PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets U... | 07/06/2010 |
| 7728631 | Phase frequency detector with pulse width control circuitry A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a... | 06/01/2010 |
| 7622960 | Metastable-resistant phase comparing circuit A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels;... | 11/24/2009 |
| 7598775 | Phase and frequency detector with zero static phase error A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PF... | 10/06/2009 |
| 7532039 | Clock signal detector A clock signal detector is provided. The device comprises a plurality of signal delayers and a plurality of flip-flops for comparing the offset range of the clock signal between two different groups, and transmitting the resulted signal to a phase compensator, which... | 05/12/2009 |
| 7532038 | Phase detecting circuit having adjustable gain curve and method thereof A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit. The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control ... | 05/12/2009 |
| 7508239 | Pattern sequence and state transition triggers A pattern sequence and state transition trigger generator provides a trigger when a specified transition from one pattern/state to another pattern/state occurs in a set of input signals. Decoders detect each specified pattern/state from the set of input signals to p... | 03/24/2009 |
| 7501861 | Phase-difference detecting apparatus and method A phase-difference detecting method is for detecting phase difference between a first signal and a second signal of the same frequency. First, generate a detection signal. Next, sample the detection signal respectively according to the first signal and the second si... | 03/10/2009 |
| 7443206 | High-frequency linear phase-frequency detector with wide-pulse outputs A circuit and method are provided for detecting a phase difference between at least two periodic signals. The circuit and method disclosed herein provide pulsed output signals with wide output pulse widths well suited for use to drive a charge-pump in a phase-locked... | 10/28/2008 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7425851 | Phase-locked loop with incremental phase detectors and a converter for combining a logical operation with a digital to analog conversion The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a ph... | 09/16/2008 |
| 7423456 | Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was... | 09/09/2008 |
| 7417470 | Phase frequency detector with a novel D flip flop Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is ... | 08/26/2008 |
| 7414446 | DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock b... | 08/19/2008 |
| 7400204 | Linear phase detector and charge pump A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference using a phase difference to charge conversion that is substantially lin... | 07/15/2008 |
| 7388408 | Phase-frequency detector capable of reducing dead zone A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sens... | 06/17/2008 |
| 7382163 | Phase frequency detector used in digital PLL system A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the s... | 06/03/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7372289 | Semiconductor integrated circuit device and power supply voltage monitor system employing it A semiconductor integrated circuit device, i.e. a reset IC(1), includes: a detection circuit (4) for detecting whether an input voltage (Vin) has risen or dropped by comparing the input voltage (Vin) with a reference voltage; a delay circuit (8)... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7368945 | Logic circuit, timing generation circuit, display device, and portable terminal When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to... | 05/06/2008 |
| 7342427 | Automatic clock based power-down circuit An apparatus and method for automatically transitioning the operation of an electronic device to a reduced power consumption state if an input reference clock signal is stopped or no longer synchronized (locked) with the operation of the electronic device. The elect... | 03/11/2008 |
| 7340631 | Drift-tolerant sync pulse circuit in a sync pulse generator A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock do... | 03/04/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7337345 | Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch w... | 02/26/2008 |
| 7332973 | Circuit and method for digital phase-frequency error detection A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output r... | 02/19/2008 |