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| Number | Title | Issue Date |
| 8040166 | Frequency multiplier In one aspect, the present invention provides a frequency multiplier. In some embodiments, the frequency multiplier includes: a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to a third terminal of the second ... | 10/18/2011 |
| 7919997 | Systems and methods for providing a clock signal Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The fre... | 04/05/2011 |
| 7759988 | Frequency multiplier A frequency multiplier is provided that includes a switching component having a plurality of differential pairs of transistors. The frequency multiplier further includes a gain stage. A common mode feedback generated by the switching component is also provided to th... | 07/20/2010 |
| 7598782 | Circuit for changing a frequency A circuit is provided for multiplying a frequency by a cascade formed of a transadmittance having a transfer characteristic and a transimpedance having a transfer characteristic. The transadmittance includes two terminals for a signal of a first frequency and the tr... | 10/06/2009 |
| 7495484 | Programmable frequency multiplier A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2n×f (n=0, 1, 2, . . . ); a se... | 02/24/2009 |
| 7436166 | Direct digital synthesizer producing a signal representing an amplitude of a sine wave The invention is directed to a digital phase detector that comprises a splitter and phase shifter to receive a signal of a device under test and produce a first signal that is substantially identical to the received signal and a second signal that is phase shifted r... | 10/14/2008 |
| 7414443 | Frequency multiplier A device is provided for multiplying the pulse frequency of a pulse train signal. The device includes input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means ... | 08/19/2008 |
| 7394299 | Digital clock frequency multiplier A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (N | 07/01/2008 |
| 7388412 | Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays... | 06/17/2008 |
| 7373113 | Frequency generation apparatus and method for data transmission A reference frequency generation method and apparatus for communication systems that transmit and receive data by use of an ultra wide band of at least two frequency groups having at least two reference frequencies. The method and apparatus generate the reference fr... | 05/13/2008 |
| 7362070 | Electric motor control system including position determination and error correction A system for controlling an electric motor includes a controller and a position indicator that provides position information regarding at least one motor component to the controller. The controller utilizes phase relationships indicative of the position information ... | 04/22/2008 |
| 7355462 | Phase lock loop and method for operating the same A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital... | 04/08/2008 |
| 7349676 | Upconverter An upconverter receives an intermediate frequency (IF) modulated signal on a port (5) and a local oscillator carrier signal at a port (6). A comb generator (13-15) generates a comb-like waveform from the carrier signal, the waveform havin... | 03/25/2008 |
| 7340624 | Clock control system and clock control method This invention relates to a clock control system including a CPU, a peripheral functional block for the CPU, a frequency multiplication circuit which multiplies the frequency of an input system clock and outputs the multiplied system clock, a plurality of frequency ... | 03/04/2008 |
| 7340233 | Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals An integrated circuit may include a receiver and/or a transmitter that performs third order sub-harmonic conversion. The integrated circuit may include a Gilbert cell active mixer with three or more serially-connected transistors in each of the mixer's four branches... | 03/04/2008 |
| 7323917 | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase gene... | 01/29/2008 |
| 7324043 | Phase shifters deposited en masse for an electronically scanned antenna A system and method for an electronically scanned antenna is provided in which phase shifters are deposited en masse along with other electronically scanned antenna components on a wafer scale substrate using a thin film process. Alternative wafer scale sizes may be... | 01/29/2008 |
| 7321751 | Method and apparatus for improving dynamic range in a communication system An apparatus for improving dynamic range includes a frequency down-conversion module that receives an input signal and a bias circuit. The bias circuit includes a first resistor and a second resistor. The first resister has a first terminal coupled to a bias point a... | 01/22/2008 |
| 7295048 | Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of... | 11/13/2007 |
| 7295824 | Frequency multiplier pre-stage for fractional-N phase-locked loops A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circui... | 11/13/2007 |
| 7271631 | Clock multiplication circuit A clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The circuit delivers an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as i... | 09/18/2007 |
| 7272527 | Method of test of clock generation circuit in electronic device, and electronic device In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic devic... | 09/18/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7254208 | Delay line based multiple frequency generator circuits for CDMA processing A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay lin... | 08/07/2007 |
| 7253842 | Locking display pixel clock to input frame rate To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured u... | 08/07/2007 |
| 7245164 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 07/17/2007 |
| 7239189 | Clock generating circuit A clock generating circuit includes a first delay circuit array, which has a plurality of delay circuits, for measuring delay of an input signal, and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction... | 07/03/2007 |
| 7236039 | Spread spectrum clock generating apparatus Disclosed is a spread spectrum clock generator comprising a phase interpolator, which receives a clock signal from a clock input terminal and a control signal (an up signal and/or down signal), for adjusting the phase of an output clock signal in accordance with sai... | 06/26/2007 |
| 7236058 | Low frequency doubler A circuit and corresponding method for doubling the frequency of an input signal, even when the input signal is of low frequency or a square wave. The input signal is applied to a phase-shifting circuit that produces a pair of output signals that are theoretically 9... | 06/26/2007 |
| 7233170 | Programmable driver delay Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a ... | 06/19/2007 |
| 7227920 | Circuit and method for correcting clock duty cycle Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clo... | 06/05/2007 |
| 7227392 | Frequency multiplier A multiplier core outputs a single-phase signal containing a frequency component having a frequency which is an even multiple of the frequency of an input signal. A differential amplifier includes first and second nMOS transistors having respective source terminals ... | 06/05/2007 |
| 7218156 | Supply tracking clock multiplier A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power con... | 05/15/2007 |
| 7215169 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 05/08/2007 |
| 7212045 | Double frequency signal generator A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An av... | 05/01/2007 |
| 7212441 | Non volatile semiconductor memory device In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the object o... | 05/01/2007 |
| 7196560 | Clock frequency multiplier and method for multiplying a clock frequency A clock frequency multiplier is provided. The clock frequency multiplier comprises a tracking circuit, a pulsing circuit, and a shaping circuit. The tracking circuit receives a clearing signal and a reference clock signal, outputs the quotient of the number of cycle... | 03/27/2007 |
| 7194667 | System for storing device test information on a semiconductor device using on-device logic for determination of test results A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are sto... | 03/20/2007 |
| 7187917 | Current interpolation in multi-phase local oscillator for use with harmonic rejection mixer A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 | 03/06/2007 |
| 7181181 | Multi-band transceiver for a wireless communication system A local oscillation signal generator and a multi-band transceiver including the local oscillation signal generator are provided. The multi-band transceiver includes a fractional-N phased locked loop (PLL), a local oscillation signal generator, and a transmitter. The... | 02/20/2007 |
