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| Number | Title | Issue Date |
| 8183896 | Resistive frequency mixing apparatus and signal processing method using the same A resistive frequency mixing apparatus includes a first frequency mixer having a source follower FET, and a second frequency mixer having a common source FET. The resistive frequency mixing apparatus perform a frequency mixing of an RF depending on an LO signal to g... | 05/22/2012 |
| 7956656 | Systems and methods for providing a clock signal Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The fre... | 06/07/2011 |
| 7830184 | Frequency multiplier A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node ... | 11/09/2010 |
| 7746128 | Clock multiplier and clock generator having the same A clock multiplier includes a phase-frequency detector, a voltage-current converter, a duty ratio control circuit, a plurality of variable delay cells and an edge combiner. The phase-frequency detector generates control signals. The voltage-current converter convert... | 06/29/2010 |
| 7741885 | Frequency multiplier A device for modifying an input signal having an input signal frequency and a duty cycle is disclosed. The device determines two separate counts for each of the high and low pulses of the input signal. One of the two counts for each of the high and low pulses is div... | 06/22/2010 |
| 7683680 | Combined phase comparator and charge pump circuit A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be ... | 03/23/2010 |
| 7535269 | Multiplier circuit A multiplier circuit includes a bias circuit which outputs a reference voltage and a bias signal, a first delay circuit which inputs an input signal and outputs a first delayed signal according to the reference voltage and the bias signal, a second delay circuit whi... | 05/19/2009 |
| 7459947 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 12/02/2008 |
| 7459946 | Circuit arrangement for generating a reference signal In a circuit arrangement for generation of a reference signal with an oscillation generator, a phase-controlled filter and a frequency multiplier are arranged downstream from the oscillation generator. The frequency multiplier is connected with an output for emissio... | 12/02/2008 |
| 7427883 | High bandwidth phase locked pool (PLL) A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses ... | 09/23/2008 |
| 7414443 | Frequency multiplier A device is provided for multiplying the pulse frequency of a pulse train signal. The device includes input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means ... | 08/19/2008 |
| 7394299 | Digital clock frequency multiplier A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (N | 07/01/2008 |
| 7388412 | Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays... | 06/17/2008 |
| 7372931 | Unit interval discovery for a bus receiver A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective ... | 05/13/2008 |
| 7372310 | Digital frequency-multiplying DLLs Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of uni... | 05/13/2008 |
| 7366937 | Fast synchronization of a number of digital clocks The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, resp... | 04/29/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7352755 | Network interface card (NIC) with phase lock rise time control generating circuit A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulse... | 04/01/2008 |
| 7342430 | Write strategy with multi-stage delay cell for providing stable delays on EFM clock Present invention provides a method and apparatus for generating multiple phase shifted clocks with clocks delayed from EFM clock. ... | 03/11/2008 |
| 7342425 | Method and apparatus for a symmetrical odd-number clock divider A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock signal having a symmetrical waveform. Finite state machines may be use... | 03/11/2008 |
| 7343507 | Input circuit and method for the operation thereof An input circuit (1′) provided with a time delay element (40), which circuit is capable of being tested by a controlled high level or low level connection, and a method for the operation thereof. The delay time of the time-delay element can be modifi... | 03/11/2008 |
| 7340233 | Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals An integrated circuit may include a receiver and/or a transmitter that performs third order sub-harmonic conversion. The integrated circuit may include a Gilbert cell active mixer with three or more serially-connected transistors in each of the mixer's four branches... | 03/04/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7331010 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 02/12/2008 |
| 7327179 | Pulse generator, optical disk writer and tuner A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator and a selecting arrangement for selecting how many of a first group of delay elements are connected in series for delaying ... | 02/05/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7319345 | Wide-range multi-phase clock generator A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respe... | 01/15/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7313210 | System and method for establishing a known timing relationship between two clock signals A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transpor... | 12/25/2007 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7302011 | Quadrature frequency doubling system The frequency doubler of the present invention operates to provide an in-phase signal and a quadrature signal, each having a frequency equal to twice the frequency of a reference signal. The in-phase and quadrature signals are based on signals that are 0 degrees, 45... | 11/27/2007 |
| 7301375 | Off-chip driver circuit and data output circuit using the same An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip... | 11/27/2007 |
| 7295048 | Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of... | 11/13/2007 |
| 7295824 | Frequency multiplier pre-stage for fractional-N phase-locked loops A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circui... | 11/13/2007 |
| 7289783 | Mixer circuits and methods with matched bias currents Embodiments of the present invention include circuits and methods for improving the spectral purity of mixer circuits. In one embodiment the present invention includes a mixer circuit including a bias circuit, the bias circuit comprising a first transistor having a ... | 10/30/2007 |
| 7285998 | Duty ratio adjusting circuit A duty ratio adjusting circuit has a differential buffer (11) to produce a pulse signal (Dout) according to an input sine wave signal (Ain) and a reference voltage. The pulse signal is inverted and filtered to be supplied to a first analog buffer (14) ... | 10/23/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7276943 | Highly configurable PLL architecture for programmable logic A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, int... | 10/02/2007 |
| 7276949 | Multiphase clock generation A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A t... | 10/02/2007 |
