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| Number | Title | Issue Date |
| 8183895 | Clock dividing circuit A clock dividing circuit includes a control logic unit and a flip-flop. The control logic unit outputs an enable signal and a data signal according to a clock signal and a division ratio. The flip-flop outputs a divided clock signal based on the clock signal, the en... | 05/22/2012 |
| 8120392 | Frequency dividing circuit A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency d... | 02/21/2012 |
| 8102194 | Dual frequency divider having phase-shifted inputs and outputs A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal di... | 01/24/2012 |
| 8093929 | Programmable digital clock signal frequency divider module and modular divider circuit A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coup... | 01/10/2012 |
| 8093928 | Signal source devices A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units.... | 01/10/2012 |
| 8085068 | Combined static and dynamic frequency divider chains using thin film transistors Frequency divider circuits and architectures, and methods of implementing and using the same, are disclosed. In one embodiment, the frequency divider circuit includes a dynamic section that receives an input signal and outputs an intermediate signal that has a frequ... | 12/27/2011 |
| 8081017 | Clock signal frequency dividing circuit and clock signal frequency dividing method To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal ... | 12/20/2011 |
| 8030975 | Method and apparatus for generating frequency divided signals A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operati... | 10/04/2011 |
| 8004319 | Programmable clock divider In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second number... | 08/23/2011 |
| 7999581 | System and a method for providing an output clock signal A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; an... | 08/16/2011 |
| 7994828 | Frequency divider, frequency dividing method thereof, and phase locked loop utilizing the frequency divider A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable del... | 08/09/2011 |
| 7973574 | Flip-flop, frequency divider and RF circuit having the same A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output... | 07/05/2011 |
| 7969209 | Frequency divider circuit Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also ... | 06/28/2011 |
| 7948279 | Clock divider There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic... | 05/24/2011 |
| 7936190 | Systems, methods and circuitry relating to frequency dividers A frequency divider can include at least one input device receiving an input signal, the at least one input device converting the input signal to a current signal; a driver stage with at least two drivers, the at least two drivers receiving the current signal from t... | 05/03/2011 |
| 7808287 | Frequency divider circuits A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a lat... | 10/05/2010 |
| 7750693 | Frequency divider including latch circuits A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source c... | 07/06/2010 |
| 7750692 | Digital divider for low voltage LOGEN Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary metal-oxide-semiconductor (CMOS), in that, it is not a true CMOS type circuitry that has no DC current dissipation, ... | 07/06/2010 |
| 7737738 | Frequency divider A frequency divider comprising, a first latch circuit and a second latch circuit, the second latch circuit being crossed-coupled to the first latch circuit. Each latch comprises a respective sense amplifier coupled to a respective latch. The sense amplifiers compris... | 06/15/2010 |
| 7719326 | Dual-modulus prescaler circuit operating at a very high frequency The dual-modulus prescaler circuit (1) is devised to operate at a very high frequency. This circuit includes an assembly formed of two dynamic D-type flip flops (12, 13), and two NAND logic gates (15, 16) arranged in negative feedback between th... | 05/18/2010 |
| 7683679 | AFSM circuit and method for low jitter PLL CMOS programmable divider A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1... | 03/23/2010 |
| 7671640 | Direct injection-locked frequency divider circuit with inductive-coupling feedback architecture A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-... | 03/02/2010 |
| 7667505 | Quadrature divide-by-three frequency divider and low voltage muller C element A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used ... | 02/23/2010 |
| 7663414 | Prescaling stage for high frequency applications A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied b... | 02/16/2010 |
| 7656205 | Dual-injection locked frequency dividing circuit A dual-injection locked frequency dividing circuit is proposed, which is designed for integration to a gigahertz signal processing circuit system for providing a frequency dividing function to gigahertz signals. The proposed circuit architecture is characterized by ... | 02/02/2010 |
| 7656204 | Divider circuit A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising... | 02/02/2010 |
| 7557621 | Divider A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the ... | 07/07/2009 |
| 7551009 | High-speed divider with reduced power consumption A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-... | 06/23/2009 |
| 7538590 | Methods and apparatus for dividing a clock signal There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true s... | 05/26/2009 |
| 7521972 | Fifty percent duty cycle clock divider circuit and method In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respec... | 04/21/2009 |
| 7518418 | Ratio granularity clock divider circuit and method In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Ith cycle to produce the input... | 04/14/2009 |
| 7518417 | Wireless transceiver components with improved IQ matching A frequency divider comprises a first differential input pair, a second differential input pair, a first capacitive element having first and second ends, a second capacitive element having first and second ends, and four current sourcing elements. The first differen... | 04/14/2009 |
| 7514970 | Decimal frequency synthesizer A frequency synthesizer and method for synthesizing decimal frequencies. The synthesizer includes a seed generator, a clock synthesizer and an output synthesizer. The clock synthesizer includes a binary accumulator in a feedback signal path using a base reference fr... | 04/07/2009 |
| 7511542 | Frequency dividing circuit A frequency dividing circuit includes: a D-type flip flop that outputs frequency-divided signal synchronized with input clock and reverse phase signal corresponding to the frequency-divided signal; a variable delay circuit that generates a delay feedback signal dela... | 03/31/2009 |
| 7471123 | Fractional-N baseband frequency synthesizer in bluetooth applications A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80... | 12/30/2008 |
| 7453293 | High frequency divider state correction circuit The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled... | 11/18/2008 |
| 7444534 | Method and apparatus for dividing a digital signal by X.5 in an information handling system An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divid... | 10/28/2008 |
| 7427883 | High bandwidth phase locked pool (PLL) A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses ... | 09/23/2008 |
| 7425850 | Quadrature divider The quadrature divider comprises a plurality of flip-flops, including at least a first flip flop and an endmost flip-flop, interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes differential in... | 09/16/2008 |
| 7424087 | Clock divider A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in syn... | 09/09/2008 |
