Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8174293 | Time to digital converter A time to digital converter includes: a delay circuit having a plurality of delay stages that delay an input clock signal in multiple stages, at least one of the delay stages being a variable delay stage; a plurality of flip flops that capture outputs of the delay s... | 05/08/2012 |
| 8013641 | Frequency synthesizer including a digital lock detector There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits;... | 09/06/2011 |
| 7948274 | Frequency generation circuitry and method A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of ... | 05/24/2011 |
| 7928773 | Multiple frequency synchronized phase clock generator Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generat... | 04/19/2011 |
| 7911242 | Signal generating apparatus, test apparatus and circuit device There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including ... | 03/22/2011 |
| 7808283 | Synchronous frequency synthesizer An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of pha... | 10/05/2010 |
| 7663411 | Semiconductor device with a logic circuit The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first ... | 02/16/2010 |
| 7609096 | Frequency synthesizer and method for constructing the same A frequency synthesizer and a method for constructing the same by using the architecture of digital process frequency loop (DPFL) are disclosed. The DPFL frequency synthesizer with the DPFL architecture includes a reference frequency divider counter, an output divid... | 10/27/2009 |
| 7443215 | Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/28/2008 |
| 7432751 | High performance signal generation A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal ... | 10/07/2008 |
| 7394297 | Logic gate with reduced sub-threshold leak current The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first ... | 07/01/2008 |
| 7383296 | Apparatus for fractional RF signal synthesis with phase modulation A method to improve the frequency resolution and phase noise of a synthesized RF signal results in superior instantaneous frequency change and phase modulation capability, wide frequency set ability, and suitability for implementation in a digital ASIC. The RF signa... | 06/03/2008 |
| 7372340 | Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The ... | 05/13/2008 |
| 7362837 | Method and apparatus for clock deskew A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to ... | 04/22/2008 |
| 7356076 | System and method supporting auto-recovery in a transceiver system A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceive... | 04/08/2008 |
| 7356107 | Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizont... | 04/08/2008 |
| 7356111 | Apparatus and method for fractional frequency division using multi-phase output VCO A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core recei... | 04/08/2008 |
| 7352862 | Encryption method, communication system, transmission device, and data input device An encryption method includes the steps of (a) generating random data including a first part and a second part, the first part specifying an operation to be performed on plain text data and the second part being used in the operation, (b) performing the specified op... | 04/01/2008 |
| 7352708 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border... | 04/01/2008 |
| 7349381 | Synchronization technique for spread spectrum frequency hopped data links and radios using the same A method of obtaining coarse synchronization in a frequency hopped/direct sequence spread spectrum (FH/DSS) time division multiple access (TDMA) data link network includes tuning the receiver to a first frequency used in the data link network. Then, signal strength ... | 03/25/2008 |
| 7349672 | Digital signal transceiver A digital signal transceiver includes a frequency modulator for outputting a high-frequency signal frequency-modulated with a digital signal input thereto, a power amplifier, an antenna terminal, and an antenna switch. The antenna switch includes a first branch port... | 03/25/2008 |
| 7345619 | Generating event signals in a radar system A radar system having a transmit signal path and a receive signal path and an event generator which is responsive to command signals provided by a digital signal processor (DSP) is described. The DSP generates command signals and provides the command signals to the ... | 03/18/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
| 7336702 | Jitter detecting apparatus and phase locked loop using the detected jitter A jitter detecting circuit and a phase locked loop using the detected jitter are provided. A jitter detecting circuit detecting a jitter value of a signal which is converted into a digital signal from an analog signal input, wherein the jitter value detecting circui... | 02/26/2008 |
| 7319349 | Semiconductor integrated circuit A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are sy... | 01/15/2008 |
| 7317694 | Method and apparatus for border node behavior on a full-duplex bus A method is disclosed for determining and communicating the existence of a hybrid bus. The method comprises the acts of determining whether the node has a connection to a Legacy link layer; if the node determines that it has a connection to a Legacy link layer, then... | 01/08/2008 |
| 7302237 | Wideband signal generators, measurement devices, methods of signal generation, and methods of signal analysis A wideband signal generator according to one embodiment of the invention includes a variable frequency source and a direct digital synthesizer. Local oscillators, signal analyzers, modulators, demodulators, and other equipment including one or more such generators a... | 11/27/2007 |
| 7295151 | Systems and methods for self-test of a radar altimeter Systems and methods for testing a signal generated by a Direct Digital Synthesizer (DDS) in a radar altimeter. In an embodiment of the method, a voltage signal derived by comparing a fixed reference frequency to a ramped frequency signal generated by the DDS based o... | 11/13/2007 |
| 7288972 | Circuitry for synthesizing an arbitrary clock signal and methods for the synthesis thereof Circuitry for synthesizing an arbitrary clock signal with minimal jitter is provided. The circuitry of this invention selectively multiplexes a sequence of two different byte patterns into a serializer, which serializes the sequence and transmits it to receiver circ... | 10/30/2007 |
| 7282967 | Fixed frequency clock output having a variable high frequency input clock and an unrelated fixed frequency reference signal A digital circuit generates very precise clock frequencies for applications that can tolerate a small degree of jitter but require exact long term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate rem... | 10/16/2007 |
| 7284025 | DDS pulse generator architecture A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table... | 10/16/2007 |
| 7283011 | Method for performing dual phase pulse modulation A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2 | 10/16/2007 |
| 7280061 | Digital-to-analog converter using a frequency hopping clock generator Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate i... | 10/09/2007 |
| 7280490 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border during the Self-ID process in a full-duplex communications system having at leas... | 10/09/2007 |
| 7280491 | Method and apparatus for border node behavior on a full-duplex bus A method relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border node comprising the acts of: determining whether a B PHY has received a Self-ID packet without... | 10/09/2007 |
| 7272620 | Frequency divider with low harmonics A frequency divider has two or more storage elements connected in a loop. One of the outputs of each storage element is connected to one of the inputs of another storage element. Each storage element provides at least one output signal having a period equal to the p... | 09/18/2007 |
| 7268594 | Direct digital synthesis with low jitter An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-... | 09/11/2007 |
| 7266617 | Method and apparatus for border node behavior on a full-duplex bus A method for determining and communicating the existence of a hybrid bus is disclosed. The method determines whether a connected node is a border node and forwards isochronous and asynchronous requests if the node is not a border node. If the node is a border node, ... | 09/04/2007 |
| 7242225 | Direct digital frequency synthesizer A frequency synthesizer according to the direct digital synthesis method is provided. The frequency synthesizer includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a mem... | 07/10/2007 |
| 7212054 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 05/01/2007 |
