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| Number | Title | Issue Date |
| 8125246 | Method and apparatus for late timing transition detection Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are de... | 02/28/2012 |
| 8067962 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal... | 11/29/2011 |
| 7990181 | Clockless return to state domino logic gate A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a second state. The domino circuit switches to a latch state and switches an output n... | 08/02/2011 |
| 7982503 | Dynamic circuit with slow mux input A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signa... | 07/19/2011 |
| 7977977 | Dynamic logic circuit with device to prevent contention between pull-up and pull-down device A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the d... | 07/12/2011 |
| 7940087 | Clockless return to state domino logic gate A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second state. The domino circuit switches to a latch state and switches an outpu... | 05/10/2011 |
| 7936185 | Clockless return to state domino logic gate A clockless return to state domino logic gate including a domino circuit and an input circuit. The domino circuit asserts s preset node and an enable node to a first logic state and asserts an output node and a reset node to a second logic state in a preset state, a... | 05/03/2011 |
| 7902878 | Clock gating system and method A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least o... | 03/08/2011 |
| 7898297 | Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a... | 03/01/2011 |
| 7855578 | Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakag... | 12/21/2010 |
| 7852121 | Domino logic circuit and pipelined domino logic circuit A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a... | 12/14/2010 |
| 7804330 | Adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said a... | 09/28/2010 |
| 7746117 | Complementary energy path adiabatic logic A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-typ... | 06/29/2010 |
| 7532036 | Semiconductor device having a pseudo power supply wiring A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wirin... | 05/12/2009 |
| 7479807 | Leakage dependent online process variation tolerant technique for internal static storage node A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable ke... | 01/20/2009 |
| 7443205 | Relatively low standby power Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or oth... | 10/28/2008 |
| 7429880 | Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS... | 09/30/2008 |
| 7429879 | Clock receiver circuit device, in particular for semi-conductor components A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver circuit device includes a first input adapted to be connected with a firs... | 09/30/2008 |
| 7411423 | Logic activation circuit Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of ... | 08/12/2008 |
| 7411432 | Integrated circuits and complementary CMOS circuits for frequency dividers An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave... | 08/12/2008 |
| 7411425 | Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the L... | 08/12/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
| 7403042 | Flip-flop, integrated circuit, and flip-flop resetting method A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a... | 07/22/2008 |
| 7400175 | Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transi... | 07/15/2008 |
| 7391232 | Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the... | 06/24/2008 |
| 7391233 | Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching devi... | 06/24/2008 |
| 7388400 | Semiconductor integrated circuits with power reduction mechanism A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit ... | 06/17/2008 |
| 7388399 | Domino logic with variable threshold voltage keeper A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contentio... | 06/17/2008 |
| 7389478 | System and method for designing a low leakage monotonic CMOS logic circuit A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly... | 06/17/2008 |
| 7382161 | Accelerated P-channel dynamic register A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low,... | 06/03/2008 |
| 7382157 | Interconnect driver circuits for dynamic logic Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driv... | 06/03/2008 |
| 7372305 | Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch outpu... | 05/13/2008 |
| 7365582 | Bootstrapped charge pump driver in a phase-lock loop A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors ... | 04/29/2008 |
| 7365575 | Gated clock logic circuit A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and ... | 04/29/2008 |
| 7365587 | Contention-free keeper circuit and a method for contention elimination A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a ... | 04/29/2008 |
| 7365578 | Semiconductor device with pump circuit In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the... | 04/29/2008 |
| 7362621 | Register file with a selectable keeper circuit A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selecti... | 04/22/2008 |
| 7363609 | Method of logic circuit synthesis and design using a dynamic circuit library The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a pre... | 04/22/2008 |
| 7362140 | Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic ... | 04/22/2008 |
| 7358775 | Inverting dynamic register with data-dependent hold time reduction mechanism Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generat... | 04/15/2008 |
