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| Number | Title | Issue Date |
| 8035420 | Semiconductor device and method for operating the same A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to ampli... | 10/11/2011 |
| 7994823 | Flip-flop circuit having scan function A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the firs... | 08/09/2011 |
| 7928770 | I/O block for high performance memory interfaces I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate sign... | 04/19/2011 |
| 7893722 | Clock control of state storage circuitry State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 1... | 02/22/2011 |
| 7733130 | Skew tolerant communication between ratioed synchronous clocks A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a... | 06/08/2010 |
| 7633314 | System and method for reducing power-on-transient current magnitude System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combi... | 12/15/2009 |
| 7567096 | Circuit device and method of controlling a voltage swing In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activat... | 07/28/2009 |
| 7504864 | Method for controlling the evaluation time of a state machine A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals eval... | 03/17/2009 |
| 7479806 | Semiconductor integrated circuit device The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first n... | 01/20/2009 |
| 7429879 | Clock receiver circuit device, in particular for semi-conductor components A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver circuit device includes a first input adapted to be connected with a firs... | 09/30/2008 |
| 7368950 | High speed transceiver with low power consumption High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data. | 05/06/2008 |
| 7363560 | Circuit for and method of determining the location of a defect in an integrated circuit According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of t... | 04/22/2008 |
| 7355454 | Energy recovery boost logic A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plur... | 04/08/2008 |
| 7352212 | Opposite-phase scheme for peak current reduction We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock ... | 04/01/2008 |
| 7348827 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmab... | 03/25/2008 |
| 7346861 | Programmable logic devices with two-phase latch circuitry Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock ... | 03/18/2008 |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second cou... | 03/11/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7332930 | Noise canceller circuit A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that ... | 02/19/2008 |
| 7323909 | Automatic extension of clock gating technique to fine-grained power gating A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at a... | 01/29/2008 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
| 7298171 | Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than trad... | 11/20/2007 |
| 7293190 | Noisy clock test method and apparatus A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and sets the internal clock signal high when the external clock signal is... | 11/06/2007 |
| 7285985 | Event-driven logic circuit A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plur... | 10/23/2007 |
| 7282957 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H lev... | 10/16/2007 |
| 7282960 | Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage... | 10/16/2007 |
| 7280628 | Data capture for a source synchronous interface Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in... | 10/09/2007 |
| 7265589 | Independent gate control logic circuitry A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combinatio... | 09/04/2007 |
| 7266707 | Dynamic leakage control circuit A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two powe... | 09/04/2007 |
| 7259594 | Electronic circuit with a chain of processing elements A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have o... | 08/21/2007 |
| 7257789 | LSI design method An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and... | 08/14/2007 |
| 7254667 | Data transfer between an external data source and a memory associated with a data processor A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 | 08/07/2007 |
| 7250789 | Pseudo-CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 07/31/2007 |
| 7245157 | Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the... | 07/17/2007 |
| 7230985 | Look-ahead decision feedback equalizing receiver A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second input signal, to provide a first and a second equalized external data... | 06/12/2007 |
| 7218160 | Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output da... | 05/15/2007 |
| 7213184 | Testing of modules operating with different characteristics of control signals using scan based techniques Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsyst... | 05/01/2007 |
| 7212039 | Dynamic logic register A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged... | 05/01/2007 |
| 7202704 | Leakage sensing and keeper circuit for proper operation of a dynamic circuit A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is conn... | 04/10/2007 |
| 7202712 | Multiphase resonant pulse generators A multiphase resonant pulse generator (74) has N groups of N−1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes... | 04/10/2007 |
