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| Number | Title | Issue Date |
| 8076956 | Relatively low standby power A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal that is an inverse of the input signal. A first inverter receives the o... | 12/13/2011 |
| 8030969 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that ... | 10/04/2011 |
| 7990180 | Fast dynamic register A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold ti... | 08/02/2011 |
| 7986166 | Clock buffer circuit A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. Th... | 07/26/2011 |
| 7961009 | Domino logic block having data holding function and domino logic including the domino logic block The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to an enable signal and a clock signal. The feedback signal is an output ... | 06/14/2011 |
| 7944242 | Semiconductor integrated circuit having insulated gate field effect transistors A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a no... | 05/17/2011 |
| 7928769 | Logic circuits with current control mechanisms Some embodiments regard a circuit comprising a current source network configured to generate a first current; a leakage circuit having a leakage current in at least two leakage conditions; the leakage currents affecting the flow of the first current; a current sourc... | 04/19/2011 |
| 7915925 | Scannable D flip-flop The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating its testability. The embodiment of the present invention provides a ... | 03/29/2011 |
| 7859310 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that ... | 12/28/2010 |
| 7772891 | Self-timed dynamic sense amplifier flop circuit apparatus and method Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path c... | 08/10/2010 |
| 7772890 | Systems and methods for dynamic logic keeper optimization Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, ... | 08/10/2010 |
| 7764087 | Low swing domino logic circuits Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be ... | 07/27/2010 |
| 7679403 | Dual redundant dynamic logic A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantia... | 03/16/2010 |
| 7667498 | Relatively low standby power A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal that is an inverse of the input signal. A first inverter receives the o... | 02/23/2010 |
| 7595665 | Clock gated circuit A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned... | 09/29/2009 |
| 7573300 | Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage ... | 08/11/2009 |
| 7570080 | Set dominant latch with soft error resiliency A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an... | 08/04/2009 |
| 7564266 | Logic state catching circuits A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative v... | 07/21/2009 |
| 7545177 | Method and apparatus for leakage current reduction Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source vo... | 06/09/2009 |
| 7541841 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that ... | 06/02/2009 |
| 7498845 | Power supply switching at circuit block level to reduce integrated circuit input leakage currents Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply cur... | 03/03/2009 |
| 7471114 | Design structure for a current control mechanism for power networks and dynamic logic keeper circuits A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. Th... | 12/30/2008 |
| 7471115 | Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu... | 12/30/2008 |
| 7443205 | Relatively low standby power Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or oth... | 10/28/2008 |
| 7427875 | Flip-flop circuit Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or... | 09/23/2008 |
| 7428568 | Symmetric cascaded domino carry generate circuit A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength for the true output is the same as the output drive strength for the ... | 09/23/2008 |
| 7417465 | N-domino output latch An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the st... | 08/26/2008 |
| 7417467 | Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H lev... | 08/26/2008 |
| 7411423 | Logic activation circuit Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of ... | 08/12/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
| 7403042 | Flip-flop, integrated circuit, and flip-flop resetting method A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a... | 07/22/2008 |
| 7391232 | Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the... | 06/24/2008 |
| 7391233 | Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching devi... | 06/24/2008 |
| 7388399 | Domino logic with variable threshold voltage keeper A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contentio... | 06/17/2008 |
| 7388470 | Comparator having small size and improved operating speed A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first dat... | 06/17/2008 |
| 7389478 | System and method for designing a low leakage monotonic CMOS logic circuit A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly... | 06/17/2008 |
| 7372305 | Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch outpu... | 05/13/2008 |
| 7373572 | System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data ... | 05/13/2008 |
| 7368953 | Buffer A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from ... | 05/06/2008 |
| 7365587 | Contention-free keeper circuit and a method for contention elimination A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a ... | 04/29/2008 |
