Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8134387 | Self-gating synchronizer A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the fir... | 03/13/2012 |
| 7977976 | Self-gating synchronizer A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the fir... | 07/12/2011 |
| 7928768 | Apparatus for metastability-hardened storage circuits and associated methods A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs. ... | 04/19/2011 |
| 7880506 | Resolving metastability A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of... | 02/01/2011 |
| 7795921 | Semiconductor integrated circuit and method of reducing noise A semiconductor integrated circuit includes a sampling unit, a delay unit, a first operating unit and a second operating unit. The sampling unit samples an input signal supplied from an external circuit in synchronization with a clock signal, and outputs the sampled... | 09/14/2010 |
| 7383370 | Arbiter circuit and signal arbitration method An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can preve... | 06/03/2008 |
| 7359468 | Apparatus for synchronizing clock and data between two domains having unknown but coherent phase A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer... | 04/15/2008 |
| 7340541 | Method of buffering bidirectional digital I/O lines A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a... | 03/04/2008 |
| 7337345 | Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch w... | 02/26/2008 |
| 7288969 | Zero clock delay metastability filtering circuit A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge ... | 10/30/2007 |
| 7276942 | Method for configurably enabling pulse clock generation for multiple signaling modes A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse ... | 10/02/2007 |
| 7274221 | Comparator circuit An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output... | 09/25/2007 |
| 7259607 | Integrated semiconductor memory with clock generation An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external cloc... | 08/21/2007 |
| 7236036 | Apparatus and method for generating pulses An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respec... | 06/26/2007 |
| 7230985 | Look-ahead decision feedback equalizing receiver A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second input signal, to provide a first and a second equalized external data... | 06/12/2007 |
| 7225283 | Asynchronous arbiter with bounded resolution time and predictable output state An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output sign... | 05/29/2007 |
| 7202704 | Leakage sensing and keeper circuit for proper operation of a dynamic circuit A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is conn... | 04/10/2007 |
| 7193430 | Semiconductor integrated circuit device with filter circuit There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after e... | 03/20/2007 |
| 7180332 | Clock synchronization circuit A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where ... | 02/20/2007 |
| 7176725 | Fast pulse powered NOR decode apparatus for semiconductor devices A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th... | 02/13/2007 |
| 7170320 | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and th... | 01/30/2007 |
| 7132858 | Logic circuit A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit... | 11/07/2006 |
| 7123674 | Reducing latency and power in asynchronous data transfers Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a sour... | 10/17/2006 |
| 7119602 | Low-skew single-ended to differential converter A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-o... | 10/10/2006 |
| 7106091 | Circuit configuration and method for detecting an unwanted attack on an integrated circuit A circuit configuration for detecting an unwanted attack on an integrated circuit has a signal line to which a clock signal is applied and at least one line pair which is respectively used to code a bit. The signal line and the at least one line pair are connected b... | 09/12/2006 |
| 7095252 | Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to ... | 08/22/2006 |
| 7091742 | Fast ring-out digital storage circuit A static storage element distorts metastable feedback signals in an unbalanced feedback loop with the resulting metastable signals eroding and being suppressed as they circulate in the loop. The element exhibits a predetermined output state subsequent to suppression... | 08/15/2006 |
| 7088144 | Conditional precharge design in staticized dynamic flip-flop with clock enable A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method. When the modified dynamic flip-flop is in a holding mode, i.e., in the c... | 08/08/2006 |
| 7081778 | Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input termina... | 07/25/2006 |
| 7075336 | Method for distributing clock signals to flip-flop circuits A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a... | 07/11/2006 |
| 7061286 | Synchronization between low frequency and high frequency digital signals A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationshi... | 06/13/2006 |
| 7053685 | Frequency signal enabling apparatus and method thereof The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pu... | 05/30/2006 |
| 7042250 | Synchronization of clock signals in a multi-clock domain A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior ... | 05/09/2006 |
| 6995585 | System and method for implementing self-timed decoded data paths in integrated circuits A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transm... | 02/07/2006 |
| 6975151 | Latch circuit having reduced input/output load memory and semiconductor chip A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals... | 12/13/2005 |
| 6963227 | Apparatus and method for precharging and discharging a domino circuit A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously. ... | 11/08/2005 |
| 6960941 | Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged intern... | 11/01/2005 |
| 6958627 | Asynchronous pipeline with latch controllers An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the ... | 10/25/2005 |
| 6949955 | Synchronizing signals between clock domains A method and apparatus to synchronize signals between different clock domains are described. ... | 09/27/2005 |
| 6943414 | Method for fabricating a metal resistor in an IC chip and related structure According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit... | 09/13/2005 |
