Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8188766 | Self-contained systems including scalable and programmable divider architectures and methods for generating a frequency adjustable clock signal The present systems and methods extend the frequency range of a clock signal generated with a phase-locked loop (PLL). The PLL receives a reference signal from a reference signal divider and a feedback signal from a feedback signal divider. The PLL generates an outp... | 05/29/2012 |
| 8188765 | Circuit and method for asynchronous pipeline processing with variable request signal delay Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bit... | 05/29/2012 |
| 8138795 | Self-aware adaptive power control system and a method for determining the circuit state The present invention provides a self-aware power control system and a method for determining the circuit state. The self-aware adaptive power control architecture comprises of a multi-mode power gating network, a current monitoring translator, a variable threshold ... | 03/20/2012 |
| 8102189 | Clock guided logic with reduced switching Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path. ... | 01/24/2012 |
| 8058905 | Clock distribution to facilitate gated clocks Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various pl... | 11/15/2011 |
| 8054103 | Synchronous clock multiplexing and output-enable A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate resp... | 11/08/2011 |
| 8040155 | Systems and methods of integrated circuit clocking Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchroni... | 10/18/2011 |
| 8035419 | High-speed standard cells designed using a deep-submicron physical effect A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or ... | 10/11/2011 |
| 8013635 | Multi-mode circuit and a method for preventing degradation in the multi-mode circuit Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the... | 09/06/2011 |
| 7994822 | Semiconductor device for synchronous communication between stacked LSI The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock puls... | 08/09/2011 |
| 7990179 | Clock distribution circuit and layout design method using same A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the firs... | 08/02/2011 |
| 7982502 | Asynchronous circuit representation of synchronous circuit with asynchronous inputs A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous... | 07/19/2011 |
| 7977975 | Apparatus for using metastability-hardened storage circuits in logic devices and associated methods An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit p... | 07/12/2011 |
| 7973565 | Resonant clock and interconnect architecture for digital devices with multiple clock networks A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to arch... | 07/05/2011 |
| 7956647 | Circuit, apparatus and method of transmitting signal A circuit includes a first wiring to transmit a first signal, an alteration element to adjust a delay amount being added to the first wiring, and a shield element to shield the alteration element from a second wiring, the second wiring transmitting a second signal. | 06/07/2011 |
| 7956648 | Output driver robust to data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A... | 06/07/2011 |
| 7952390 | Logic circuit having gated clock buffer A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, ... | 05/31/2011 |
| 7952391 | Digital noise filter A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit s... | 05/31/2011 |
| 7944241 | Circuit for glitchless switching between asynchronous clocks A circuit for glitchless switching between asynchronous clocks includes a select circuit and enable circuits. The select circuit receives a selection signal for selecting one of the clock input signals and to generate enabling signals for activating the correspondin... | 05/17/2011 |
| 7932750 | Dynamic domino circuit and integrated circuit including the same A dynamic domino circuit includes a clock generator and a domino circuit. The clock generator generates a pulse signal and a plurality of internal clock signals based on a global clock signal. Phases of the plurality of internal clock signals are sequentially delaye... | 04/26/2011 |
| 7924057 | Logic system for DPA resistance and/or side channel attack resistance DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic ... | 04/12/2011 |
| 7924058 | Nonvolatile programmable logic circuit A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPG... | 04/12/2011 |
| 7919989 | Circuit architecture for effective compensating the time skew of circuit A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuit... | 04/05/2011 |
| 7915924 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT porti... | 03/29/2011 |
| 7902877 | Digital sampling mixer with multiphase clocks A multiphase clock generates pulses at a rate much higher than the clock frequency. ... | 03/08/2011 |
| 7902876 | Method and device for generating a digital data signal and use thereof In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data ... | 03/08/2011 |
| 7898296 | Distribution and synchronization of a divided clock signal Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed c... | 03/01/2011 |
| 7893721 | Dual rail domino circuit and logic circuit In a dual rail domino circuit 3 using a combination of a domino circuit 1 for outputting positive logic and a domino circuit 2 for outputting negative logic, an AND 4 and a NAND 5 as members for simultaneously fixing an output of t... | 02/22/2011 |
| 7888970 | Switch controlling circuit, switch circuit utilizing the switch controlling circuit and methods thereof A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first ... | 02/15/2011 |
| 7888971 | Verification support system and method A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter cloc... | 02/15/2011 |
| 7884649 | Selection of optimal clock gating elements Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation o... | 02/08/2011 |
| 7880505 | Low power reconfigurable circuits with delay compensation According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output si... | 02/01/2011 |
| 7880504 | Logic stages with inversion timing control A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversi... | 02/01/2011 |
| 7859308 | Reconfigurable logic cell made up of double-gate MOSFET transistors Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be proces... | 12/28/2010 |
| 7859309 | Clock tree distributing method A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-... | 12/28/2010 |
| 7847595 | Input circuit and semiconductor integrated circuit comprising the input circuit A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a tri... | 12/07/2010 |
| 7825696 | Even-number-stage pulse delay device The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring... | 11/02/2010 |
| 7816950 | Semiconductor integrated circuit Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data h... | 10/19/2010 |
| 7808279 | Low power, self-gated, pulse triggered clock gating cell A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The ... | 10/05/2010 |
| 7795920 | Semiconductor integrated circuit A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and t... | 09/14/2010 |
