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| Number | Title | Issue Date |
| 5059831 | Buffer circuit with an electrostatic protector A buffer circuit comprises an interface node, a bipolar transistor having a collector connected to a first power source, an emitter connected to a second power source, and a base, for transferring a signal supplied to and from the interface node, and a di... | 10/22/1991 |
| 5045724 | Circuit for limiting the short circuit output current A TTL gate (22) includes a current generating circuit (24) comprising an NPN transistor (30) having its base coupled to a diode (24) and its emitter coupled to one of the gate's output transistors (14). Transistor (30) enables diode (24) to deliver a high... | 09/03/1991 |
| 5036225 | TTL-ECL level converting circuit A TTL-ECL converting circuit comprises a Schottky barrier diode, the cathode of which is connected to an input terminal receiving a TTL signal and the anode of which is connected to a first resistor, the other end of which is connected to a high voltage s... | 07/30/1991 |
| 4978869 | ESD resistant latch circuit A latch circuit which is resistant to electrostatic discharge includes four cross-coupled NOR gate pairs located in the four corners of an integrated circuit chip, and a fifth cross-coupled NOR gate pair positioned generally in the center of the integrate... | 12/18/1990 |
| 4942320 | Transistor circuit with improved ray resistant properties A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the re... | 07/17/1990 |
| 4935646 | Fully static CMOS cascode voltage switch logic systems A static, single-ended cascode voltage switch logic system arranged in a tree with multiple levels. Each level of each branch of the tree is comprised of a complementary pair. The invention is preferrably implemented in CMOS, so that each complementary pa... | 06/19/1990 |
| 4890018 | Bipolar-complementary metal oxide semiconductor circuit A bipolar-complementary metal oxide semiconductor circuit includes a p-channel MOS transistor, and an n-channel MOS transistor, first and second bipolar transistors. A base of the first bipolar transistor is connected to a negative power source through th... | 12/26/1989 |
| 4868420 | Flip-flop circuit An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first l... | 09/19/1989 |
| 4857763 | MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased Semiconductor integrated circuit of the present invention comprises a signal output terminal, a load circuit connected to the signal output terminal, a transistor circuit which is constituted by at least one first channel MOS transistor and has an output ... | 08/15/1989 |
| 4771190 | Emitter coupled logic circuit provided with pull-down resistors at respective bases of input transistors An ECL circuit includes a plurality of input terminals, a current source, a reference transistor having an emitter connected to the current source, a base receiving a reference voltage and a collector connected to a first resistor, a plurality of input tr... | 09/13/1988 |
| 4748594 | Integrated circuit device having a memory and majority logic An integrated circuit device having a memory. A plurality of identical versions of a given piece of data may be stored at different addresses in the memory, and portions thereof read out in time-division fashion through a reduced number of sense amplifier... | 05/31/1988 |
| 4748350 | Emitter-coupled logic circuit An emitter-coupled logic (ECL) circuit having a pull-down resistor and including a breakdown protecting structure. Such breakdown occurs in an input transistor for receiving input data when an excess reverse voltage is applied across the emitter and base ... | 05/31/1988 |
| 4717846 | Tri-state output circuit provided with means for protecting against abnormal voltage applied to output terminal An output circuit protected by an abnormal voltage supplied at an output terminal is disclosed. The output circuit comprises a first switching circuit includes first and second transistors connected in series for providing an output terminal with a first ... | 01/05/1988 |
| 4704547 | IGFET gating circuit having reduced electric field degradation As integrated field effect devices are scaled to smaller dimensions, the electric field in the channel increases for a constant operating voltage. This induces "hot electron" effects that reduce device reliability. The present invention reduces the voltag... | 11/03/1987 |
| 4686384 | Fuse programmable DC level generator A high reliability, low power fuse programmable DC level generator is implemented by providing at least one fuse in each branch of a resistive bridge such that programming of the level generator results in providing a blown fuse in the current path and as... | 08/11/1987 |
| 4612457 | Current limiting output buffer for integrated circuit An output buffer in an MOS integrated circuit is adapted to provide high output currents to meet high performance requirements under varying operating conditions and has voltage responsive MOS means limiting output current under certain operating conditio... | 09/16/1986 |
| 4531065 | Current injection type logical operation circuit arrangement including a I2 L circuit device comprising I2 L elements A I2 L circuit device including logical operation circuits comprising I2 L elements, wherein when main power supply is interrupted, an injector current is injected from an auxiliary current source circuit into part of the I2 | 07/23/1985 |
| 4523106 | Integrated circuit having predetermined outer to inner cell pitch ratio An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells f... | 06/11/1985 |
| 4511812 | Programmable logic array, including an arrangement for invalidating faulty and term outputs A programmable logic array comprises an AND array for producing AND term outputs on a plurality of AND term lines, an OR array which receives the AND term output of the AND array as inputs thereto, and an AND term disregarding array connected to the AND t... | 04/16/1985 |
| 4477741 | Dynamic output impedance for 3-state drivers This describes a tristate driver circuit designed such that it will not be destroyed by excessive high voltage conditions when two such drivers are connected to a bus at the same time. The circuit accomplishes this with parallel high current, low impedanc... | 10/16/1984 |
| 4382197 | Logic having inhibit mean preventing erroneous operation circuit A logic circuit operable without erroneous operation is disclosed. The logic circuit comprises a first and a second switching transistor operating in response to the same signal, a first logic gate including an input transistor receiving a signal derived ... | 05/03/1983 |
| 4380710 | TTL to CMOS Interface circuit An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is... | 04/19/1983 |
| 4370570 | Circuit for minimizing radiation A circuit is described for substantially reducing the level of radiation from another circuit such as a clock circuit that might be used in a computing device. By maintaining the current drawn by the clock driver from the power supply at a constant level,... | 01/25/1983 |
| 4336468 | Simplified combinational logic circuits and method of designing same A logic circuit and method for implementing a given, partially symmetric Boolean function f(x1 -xn) which is pairwise symmetric with respect to at least one pair xi xj of variables such that the function is inva... | 06/22/1982 |
| 4239980 | Integrated circuit having an operation voltage supplying depletion type MISFET of high breakdown voltage structure A depletion type MISFET is connected between a power voltage supply line of a transistor logic circuit block and a power source voltage terminal. The gate electrode of the depletion type MISFET is connected to a reference voltage. The transistor logic cir... | 12/16/1980 |
| 4223395 | Volatile memory hold device A volatile memory hold device comprising power terminals to which a power source is connectable, a volatile memory connected to the power terminals which serves as input power terminals therefor, and a charge-and-discharge circuit connected to the power t... | 09/16/1980 |
| 4206368 | Signal isolating technique In a system wherein a single input signal is transmitted via a plurality of output signal channels for various signal processing and control functions, optical isolating circuits in combination with current limiting resistors provide operational isolation... | 06/03/1980 |
| 4197471 | Circuit for interfacing between an external signal and control apparatus An input/output interface for a digital controller including an optical isolator coupling an input portion which formats an external signal to make it compatible with the optical isolator and an output portion comprising an RC network connected to a thres... | 04/08/1980 |
| 4139787 | Line-addressable random-access memory decoupling apparatus A decoupling apparatus for a charge-coupled device line-addressable random-access memory includes a series of bipolar transistors, the bases of which are connected to output lines from the CCD LARAM. The emitters of the bipolar transistors, connected toge... | 02/13/1979 |
