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| Number | Title | Issue Date |
| 8183887 | High speed signaling system with adaptive transmit pre-emphasis A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to genera... | 05/22/2012 |
| 8138794 | Output slew rate control This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are con... | 03/20/2012 |
| 8125245 | Circuitry for matching the up and down impedances of a voltage-mode transmitter Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs o... | 02/28/2012 |
| 8035418 | Output driver An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving trans... | 10/11/2011 |
| 8022731 | Advanced repeater with duty cycle adjustment An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selec... | 09/20/2011 |
| 8004313 | Methods, devices, and systems for a high voltage tolerant buffer Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality... | 08/23/2011 |
| 8004314 | Semiconductor device A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal an... | 08/23/2011 |
| 7973564 | High load driving device A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effec... | 07/05/2011 |
| 7961008 | Data output driving circuit of semiconductor memory apparatus A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving un... | 06/14/2011 |
| 7956646 | Buffer circuit and control method thereof The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from bec... | 06/07/2011 |
| 7919988 | Output circuit and driving method thereof An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving un... | 04/05/2011 |
| 7902875 | Output slew rate control This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are con... | 03/08/2011 |
| 7808278 | Driver calibration methods and circuits Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without... | 10/05/2010 |
| 7795919 | Transmitter driver circuit in high-speed serial communications system A driver circuit in a high-speed serial communications system changes an input data signal into a differential signal. A first output terminal is connected to a predetermined power supply voltage through a first pullup resistance circuit and to a grounding voltage t... | 09/14/2010 |
| 7782091 | Apparatus, system, and method for driver circuits Some embodiments include an output driver having a first circuit to provide a plurality of first parallel circuit paths between an output node and a first supply node, a second circuit to provide a plurality of second parallel circuit paths between the output node a... | 08/24/2010 |
| 7768312 | Semiconductor device and driver control method A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of ... | 08/03/2010 |
| 7714618 | Output driver circuit with output preset circuit and controlling method thereof having lower power consumption The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signa... | 05/11/2010 |
| 7705633 | Advanced repeater with duty cycle adjustment An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selec... | 04/27/2010 |
| 7667493 | Data transmitter Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the fi... | 02/23/2010 |
| 7642811 | Slew rate controlled output driver for use in semiconductor device An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an ... | 01/05/2010 |
| 7635991 | Output buffer strength trimming Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more st... | 12/22/2009 |
| 7612585 | Pull-up circuit for an input buffer An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage l... | 11/03/2009 |
| 7605611 | Methods, devices, and systems for a high voltage tolerant buffer Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up ... | 10/20/2009 |
| 7586332 | Off-chip driver A driver includes a plurality of first PMOS transistors, a first resistor, a amplifier, a second PMOS transistor and a second resistor. The amplifier herein receives a reference voltage and outputs a regulating voltage. The above-mentioned reference voltage is produ... | 09/08/2009 |
| 7521969 | Switch sequencing circuit systems and methods Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data si... | 04/21/2009 |
| 7511534 | Circuits, devices, systems, and methods of operation for a linear output driver Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current pat... | 03/31/2009 |
| 7477075 | CMOS output driver using floating wells to prevent leakage current An I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal ... | 01/13/2009 |
| 7471113 | Low crowbar current slew rate controlled driver A slew rate controlled circuit driver generates a binary output signal with strong direct current (DC) characteristics based on a received binary logic signal, while minimizing crowbar current. The slew rate controlled circuit driver may include a first driver with ... | 12/30/2008 |
| 7446572 | Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss refer... | 11/04/2008 |
| 7443193 | Techniques for providing calibrated parallel on-chip termination impedance Techniques are provided for calibrating parallel on-chip termination (OCT) impedance circuits. An on-chip termination (OCT) calibration circuit generates first calibration codes and second calibration codes. The first calibration codes control the conductive states ... | 10/28/2008 |
| 7443204 | Common-mode noise-reduced output transmitter Various embodiments provide a high speed serial transmitter that utilizes a current-mode driver comprising a main driver and a de-emphasis driver. The de-emphasis driver includes a first driver circuit and a complementary second driver circuit that is operably coupl... | 10/28/2008 |
| 7436215 | Transmitter In some embodiments, a transmitter includes a first circuit coupled to an input port of the transmitter, and a second circuit coupled to the first circuit and to an output port of the transmitter, wherein the first circuit is sized with respect to the second circuit... | 10/14/2008 |
| 7432741 | Controllable pre-distortion for transmitter circuitry on programmable logic device integrated circuits Transmitter driver circuitry includes multiple output driver stages, each of which receives a respective differently-phased version of an output signal for application to an output node of the circuitry. Each stage includes a primary current source. The circuitry al... | 10/07/2008 |
| 7429878 | Apparatus for controlling drive current in semiconductor integrated circuit devices A circuit device for variously controlling a current drive capacity of a semiconductor IC device as required by the user. A circuit device, capable of preventing a semiconductor IC device from failing to drive an external device, preventing an operational speed of t... | 09/30/2008 |
| 7423454 | High speed signaling system with adaptive transmit pre-emphasis A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to genera... | 09/09/2008 |
| 7420395 | Output buffer circuit and system including the output buffer circuit An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes ... | 09/02/2008 |
| 7420394 | Latching input buffer circuit with variable hysteresis An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes fou... | 09/02/2008 |
| 7417452 | Techniques for providing adjustable on-chip termination impedance Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination imp... | 08/26/2008 |
| 7417460 | Multi-standard transmitter A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input termi... | 08/26/2008 |
| 7408377 | Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding tra... | 08/05/2008 |
