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| Number | Title | Issue Date |
| 7212033 | High speed transient immune differential level shifting device A level shifting device having an input side operating at a first voltage level, an output side operating at a second voltage level and a level shifting circuit which connects the input and output sides. The input circuit receives an input signal referenced to the f... | 05/01/2007 |
| 7212038 | Line driver for transmitting data A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a ... | 05/01/2007 |
| 7212034 | Current mode signaling in electronic data processing circuit An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. ... | 05/01/2007 |
| 7208993 | Input current leakage correction for multi-channel LVDS front multiplexed repeaters A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of d... | 04/24/2007 |
| 7205809 | Low power bus-hold circuit A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a first output of the first inverter and a second input coupled to a second output of the first inverter, ... | 04/17/2007 |
| 7205793 | Self-programmable bidirectional buffer circuit and method The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes.... | 04/17/2007 |
| 7202706 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 04/10/2007 |
| 7202701 | Input/output circuit for handling unconnected I/O pads A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration sign... | 04/10/2007 |
| 7202710 | Apparatus and method for handling interdevice signaling An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting... | 04/10/2007 |
| 7199681 | Interconnecting of digital devices In some embodiments, a first conducting line, having a characteristic impedance, connects to a digital device while a second conducting line, also having a characteristic impedance, connects to another digital device. An impedance pathway connects the two conducting... | 04/03/2007 |
| 7199728 | Communication system with low power, DC-balanced serial link A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set... | 04/03/2007 |
| 7199617 | Level shifter A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode st... | 04/03/2007 |
| 7199614 | Over-voltage tolerant bus hold circuit and method therefor In one embodiment a bus hold circuit decouples an inverter of the bus hold circuit from an operating voltage responsively to an input receiving a signal having a voltage that is approximately equal to or greater than the value of the operating voltage. ... | 04/03/2007 |
| 7199616 | Method and apparatus to generate break before make signals for high speed TTL driver A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in ... | 04/03/2007 |
| 7196942 | Configuration memory structure A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which terminate at the input of a succeeding buffer. The first buffer includes pr... | 03/27/2007 |
| 7197591 | Dynamic lane, voltage and frequency adjustment for serial interconnect A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The numbe... | 03/27/2007 |
| 7196556 | Programmable logic integrated circuit devices with low voltage differential signaling capabilities A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used indivi... | 03/27/2007 |
| 7196551 | Current mode logic buffer Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltag... | 03/27/2007 |
| 7196550 | Complementary CMOS driver circuit with de-skew control A circuit for driving a pair of input signals to form driven output signals while reducing the amount of skew between the driven output signals. In one embodiment, a driver circuit includes a first set of drivers connected in series and receiving the first input sig... | 03/27/2007 |
| 7196546 | Low-swing bus driver and receiver According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-... | 03/27/2007 |
| 7196557 | Multitap fractional baud period pre-emphasis for data transmission Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power co... | 03/27/2007 |
| 7196548 | Single ended current-sensed bus with novel static power free receiver circuit A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response ... | 03/27/2007 |
| 7193441 | Single gate oxide I/O buffer with improved under-drive feature A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first sup... | 03/20/2007 |
| 7190195 | Input circuit and output circuit An input circuit is provided which prevents malfunctioning of a function circuit during a power source voltage rise without the need of a separate Under Voltage Lock Out (UVLO) circuit. The input circuit includes a first transistor which receives an input terminal s... | 03/13/2007 |
| 7190209 | Low-power high-performance integrated circuit and related methods An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on an... | 03/13/2007 |
| 7190719 | Impedance controlled transmitter with adaptive compensation for chip-to-chip communication A method and apparatus for adjusting a frequency characteristic of a signal is provided. A transmitter circuit uses a driver circuit and a filter to generate the signal. The frequency characteristic of the signal is adjusted, or “equalized,” using a replica driv... | 03/13/2007 |
| 7190191 | Over-voltage tolerant input buffer having hot-plug capability An input buffer circuit and associated method operable in a normal mode and a hot-plug mode. In one example, the input buffer has an input and a buffer output, and the input buffer may include a pull-up path coupled between a first circuit supply and the buffer outp... | 03/13/2007 |
| 7187208 | Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchroni... | 03/06/2007 |
| 7187710 | Low power pulse signaling A system for communicating between integrated circuits is disclosed. The system includes a driver having an input and an output. In response to a logic transition from a first logic state to a second logic state at the driver input, the driver output transitions fro... | 03/06/2007 |
| 7187206 | Power savings in serial link transmitters Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently t... | 03/06/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7187909 | Current mode transmitter A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal... | 03/06/2007 |
| 7187212 | System and method for providing a fast turn on bias circuit for current mode logic transmitters A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacit... | 03/06/2007 |
| 7183805 | Method and apparatus for multi-mode driver Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted t... | 02/27/2007 |
| 7183806 | Output circuit Since voltages of two input terminals of an output unit having an online download function are decided by voltages which are not correlative to each other, a value of an incoming current on the start-up becomes large. The present invention solves the problem of turn... | 02/27/2007 |
| 7183804 | Process and device for outputting a digital signal To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a r... | 02/27/2007 |
| 7183803 | Input device for a semiconductor device Disclosed is an input device for a semiconductor device that optimizes the performance characteristic of the semiconductor device using off-chip driver information. The input device includes at least two buffers, connected in parallel to an electrostatic discharge (... | 02/27/2007 |
| 7185175 | Configurable bi-directional bus for communicating between autonomous units Processing units (PUs) are coupled with a gated bi-directional bus structure that allows the PUs to be cascaded. Each PUn has communication logic and function logic. Each PUn is physically coupled to two other PUs, a PUp and a PUf. The communication logic receives L... | 02/27/2007 |
| 7183809 | Current mode transmitter capable of canceling channel charge error A current mode transmitter includes a first sink current path, through which a current flows from an output port according to a first bias voltage, a charge error canceller, which supplies a current from a high power supply voltage to a current control port in respo... | 02/27/2007 |
| 7180331 | Voltage tolerant structure for I/O cells An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the g... | 02/20/2007 |
