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| Number | Title | Issue Date |
| 7397281 | Input/output circuit of semiconductor memory device and input/output method thereof An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal l... | 07/08/2008 |
| 7391229 | Techniques for serially transmitting on-chip termination control signals Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calib... | 06/24/2008 |
| 7391231 | Switch selectable terminator for differential and pseudo-differential signaling An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three different... | 06/24/2008 |
| 7391239 | Bus driver circuit A solution for increasing the switching speed of a bus driver circuit includes a pair of transistors controlled by a pair of control circuits. Pumping circuits are placed between the control electrodes of the transistors to speed up the conduction of one of the tran... | 06/24/2008 |
| 7385424 | High-speed differential receiver A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and ... | 06/10/2008 |
| 7382153 | On-chip resistor calibration for line termination A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. Th... | 06/03/2008 |
| 7382160 | Differential output circuit with reduced differential output variation In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a se... | 06/03/2008 |
| 7383373 | Deriving corresponding signals Apparatus used in deriving corresponding signals includes first and second circuitry. The first circuitry derives, from a source-terminated first signal driven from a Peripheral Control Interface (PCI) Express compatible source, an AC-coupled second signal. The seco... | 06/03/2008 |
| 7378877 | Output buffer circuit An output buffer with a pre-emphasis function to deliver a logic signal to a transmission line as a distributed constant circuit includes a first buffer to receive a first signal assigning a logical value to a logic signal to thereby drive the transmission line, a s... | 05/27/2008 |
| 7375556 | Advanced repeater utilizing signal distribution delay An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop ... | 05/20/2008 |
| 7372313 | Variable impedance circuit and apparatus comprising said variable impedance circuit A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance an... | 05/13/2008 |
| 7372388 | A/D converter, A/D converter control method, and A/D converter connection method The present invention is intended to provide an A/D converter making it possible to reduce the power consumption of an output interface. The A/D converter includes an output current value designation register that holds a value sent from an upper-level unit, and an ... | 05/13/2008 |
| 7372303 | Semiconductor integrated circuit A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and ... | 05/13/2008 |
| 7372292 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 05/13/2008 |
| 7372301 | Bus switch circuit and interactive level shifter A bus switch circuit includes a switch element having two terminals whose electrical connection is controlled when a control signal is input into a control terminal. The bus switch circuit further includes a first pull-up resistor and first switch circuit, a second ... | 05/13/2008 |
| 7372288 | Test apparatus for testing multiple electronic devices There is disclosed a test apparatus including a driver that outputs a test signal, a first switch that is provided between the driver and a terminal of the first device under test, a second switch that is provided between the driver and a terminal of the second devi... | 05/13/2008 |
| 7368938 | Input termination circuitry with high impedance at power off An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and ... | 05/06/2008 |
| 7368949 | Output driver and output driving method for enhancing initial output data using timing An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at ... | 05/06/2008 |
| 7368952 | Output buffer circuit An output buffer circuit includes a first output buffer section and a second output buffer section. The first output buffer section includes complementary semiconductors. The second output buffer section includes complementary semiconductors and is connected in para... | 05/06/2008 |
| 7368950 | High speed transceiver with low power consumption High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data. | 05/06/2008 |
| 7368951 | Data transmission circuit and data transmission method with two transmission modes In a data transmission circuit according to the present invention, selection circuits alternately switch between transistors of a main buffer and transistors of a dummy buffer. In high-speed data transmission, a H/L transmission switch circuit outputs high-speed dat... | 05/06/2008 |
| 7365570 | Pseudo-differential output driver with high immunity to noise and jitter Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage t... | 04/29/2008 |
| 7365571 | Input buffer with wide input voltage range The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage. ... | 04/29/2008 |
| 7365572 | Multipath input buffer circuits Provided is a multi-path input buffer circuit, which passes a signal input to a semiconductor device through different paths in consideration of the voltage level of the input signal. The multi-path input buffer circuit includes an input buffer stage, which can be d... | 04/29/2008 |
| 7365582 | Bootstrapped charge pump driver in a phase-lock loop A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors ... | 04/29/2008 |
| 7365573 | Mixed-voltage interface and semiconductor integrated circuit A mixed-voltage interface transfers signals serially between a pair of circuit blocks operating at different voltage levels in a semiconductor integrated circuit. Control, address, and data signals are multiplexed onto a common signal line. The number of necessary s... | 04/29/2008 |
| 7362145 | Input/output circuit and input/output device An input/output circuit has an output terminal, a first transistor, a second transistor, a pulse generator, and a bias circuit. The first transistor drives the output terminal based on a predetermined signal. The second transistor controls a potential of the gate of... | 04/22/2008 |
| 7362146 | Large supply range differential line driver A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may... | 04/22/2008 |
| 7362131 | Integrated circuit including programmable logic and external-device chip-enable override control An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring i... | 04/22/2008 |
| 7358774 | Output driver circuit with pre-emphasis function In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing t... | 04/15/2008 |
| 7358780 | Low voltage differential signal driver with high power supply rejection ration A LVDS (Low Voltage Differential Signal) driver with a high PSRR (Power Supply Rejection Ration) includes a first current source for providing a working current, a switch unit for receiving the working current and determining the current directions of an output curr... | 04/15/2008 |
| 7355447 | Level shifter circuit A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a... | 04/08/2008 |
| 7355449 | High-speed serial data transmitter architecture Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pr... | 04/08/2008 |
| 7355448 | Semiconductor memory device for internally controlling strength of output driver Provided is a semiconductor memory device that is capable of internally controlling a strength of an output driver. The semiconductor memory device includes: an OCD (off chip driver) control signal generator for decoding EMRS and addresses to generate a plurality of... | 04/08/2008 |
| 7355452 | High speed differential receiver with an integrated multiplexer input A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP... | 04/08/2008 |
| 7353308 | Avoiding oscillation in self-synchronous bi-directional communication system In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to... | 04/01/2008 |
| 7352207 | Output driver with common mode feedback A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differen... | 04/01/2008 |
| 7352211 | Signal history controlled slew-rate transmission method and bus interface transmitter A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis... | 04/01/2008 |
| 7352204 | Automatic skew correction for differential signals A skew correction system incorporated into a transmitter forwarding a differential signal on a differential lane monitors returning signal reflections when the receiving end of the differential lane is appropriately terminated. Based on an analysis of the reflection... | 04/01/2008 |
| 7352815 | Data transceiver and method for equalizing the data eye of a differential input data signal Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye o... | 04/01/2008 |
