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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 7127003 | Method and apparatus for communicating information using different signaling types Systems, methods, apparatuses, and arrangements enable information to be communicated across a link using different types of signaling. For example, a first type of information is communicated across a bus using a first type of signaling while a second type of infor... | 10/24/2006 |
| 7126385 | Differential inverter circuit An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a se... | 10/24/2006 |
| 7126394 | History-based slew rate control to reduce intersymbol interference In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate wil... | 10/24/2006 |
| 7126408 | Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 10/24/2006 |
| 7126369 | Transceiver providing high speed transmission signal using shared resources and reduced area A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifi... | 10/24/2006 |
| 7126987 | Method and system for a fast serial transmit equalization scheme A transmitting device to send an input signal in a channel includes an equalization system. The equalization system includes a decision subsystem to determine when adjustments need to be made based on the frequency of 0s or 1s in the input signal. The equalization s... | 10/24/2006 |
| 7123048 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 10/17/2006 |
| 7123055 | Impedance-matched output driver circuits having coarse and fine tuning control Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein responsive to a ... | 10/17/2006 |
| 7123099 | Two-stage amplifier with series L-R coupling network A two-stage amplifier that includes a first stage and a second stage and a first component and a second component coupled in series between the first and second stages. The first component is selected to provide AC decoupling of the first and second stages and the s... | 10/17/2006 |
| 7123047 | Dynamic on-die termination management A dynamic on-die termination circuit for a read-only node is disclosed herein. ... | 10/17/2006 |
| 7119549 | Output calibrator with dynamic precision An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver... | 10/10/2006 |
| 7119580 | Repeater circuit with high performance repeater mode and normal repeater mode Repeater circuit with high performance repeater mode and normal repeater mode is provided and described. In one embodiment, switches are set to a first switch position to operate repeater circuit in the high performance repeater mode. In another embodiment, switches... | 10/10/2006 |
| 7119601 | Backgate pull-up for PMOS pass-gates The pass-gate circuit with backgate pull-up includes: a pass-gate transistor coupled between a first port and a second port; a backgate pull-up transistor coupled between a back gate of the pass-gate transistor and a gate of the pass-gate transistor; a first MOS tra... | 10/10/2006 |
| 7119839 | High resolution CMOS circuit using a matched impedance output transmission line Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero voltage. The impedances are matched by setting bias currents. ... | 10/10/2006 |
| 7116129 | Temperature-compensated output buffer method and circuit A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with ... | 10/03/2006 |
| 7116539 | Fast CMOS matched impedance DC write current driver for preamplifiers A driver circuit includes a CMOS stage and switch functionalities for performing certain tasks. One task is to selectively block exposure of the CMOS stage to reference voltage(s). Another task is to selectively protect the CMOS stage during transient operation. Yet... | 10/03/2006 |
| 7113002 | Transmission cable structure for GHz frequency band signals and connector used for transmission of GHz frequency band signals A differential signal transmission cable structure for transmitting differential signals having GHz frequency band in the present invention is provided with a differential signal transmission pair cable 30 connecting a driver circuit 23a and a r... | 09/26/2006 |
| 7112996 | Level shifter for detecting grounded power-supply and level shifting method A level shifter includes an input buffer, a level shifting circuit, a voltage level detecting circuit, an output buffer and a reference logic circuit. The input buffer buffers a small range input signal to output a small range signal. The level shifting circuit tran... | 09/26/2006 |
| 7113001 | Chip to chip interface A chip to chip interface comprises a driver configured to provide a first signal in response to a change in first data at one edge of a clock signal and a second signal in response to a change in second data at another edge of the clock signal. The chip to chip inte... | 09/26/2006 |
| 7109744 | Programmable termination with DC voltage level control Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip... | 09/19/2006 |
| 7109743 | Integrated circuit output driver circuitry with programmable preemphasis Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O ci... | 09/19/2006 |
| 7106095 | Circuit for compensating for the declination of balanced impedance elements and a frequency mixer Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second i... | 09/12/2006 |
| 7107019 | Methods of operating microelectronic devices, and methods of providing microelectronic devices Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices are described. In one embodiment, a microelectronic device includes a microelectronic package which provides a housing within which integrated cir... | 09/12/2006 |
| 7106105 | High voltage integrated circuit driver with a high voltage PMOS bootstrap diode emulator A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, ... | 09/12/2006 |
| 7106094 | Method and topology for improving signal quality on high speed, multi-drop busses Aspects for improving signal quality on high speed, multi-drop busses are described. The aspects include coupling a source device directly to multiple load devices, wherein there are no resistance components coupled in series between the source device and the multip... | 09/12/2006 |
| 7106092 | Semiconductor device with bus terminating function The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance w... | 09/12/2006 |
| 7101770 | Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabr... | 09/05/2006 |
| 7102389 | Voltage translator with data buffer A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An o... | 09/05/2006 |
| 7102545 | Simultaneous bidirectional input/output circuit Disclosed is a data detector for detecting data placed on a bi-directional data channel having two nodes. The data on the data channel is a combination of data placed on the data channel at both nodes. The data detector at the first node compares data received from ... | 09/05/2006 |
| 7103512 | USB eye pattern test mode A special test mode is incorporated within a USB transceiver of a digital system, and when the special test mode is activated, USB eye pattern test data signal waveforms, e.g., a continuous stream of USB state transitions (defined by the USB specification) are trans... | 09/05/2006 |
| 7099416 | Single ended termination of clock for dual link DVI receiver A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock sign... | 08/29/2006 |
| 7098833 | Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid... | 08/29/2006 |
| 7098694 | Overvoltage tolerant input buffer When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transisto... | 08/29/2006 |
| 7098701 | Receiving apparatus and transmission apparatus utilizing the same A first receiving terminal and a second receiving terminal are connected to a first signal transmission line and a second signal transmission line, respectively, and receive the input of transmission signals. A first resistor and a second resistor convert current si... | 08/29/2006 |
| 7095245 | Internal voltage reference for memory interface Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pul... | 08/22/2006 |
| 7095788 | Circuit for facilitating simultaneous multi-directional transmission of multiple signals between multiple circuits using a single transmission line An encoding element (109, 111, 113) and a decoding arrangement (110, 112, 114) is included with each separate circuit (104, 105, 106) in a system (100) of circuits which must communicate digital signals with each other. The encoding devic... | 08/22/2006 |
| 7095246 | Variable impedance output buffer An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), ... | 08/22/2006 |
| 7095250 | Single wire bus communication system with method for handling simultaneous responses from multiple clients A single wire bus communication system comprises a bus wire, a host device, and at least one client device, with each host and client device having pull-up and pull-down transistors to pull the bus wire “high” or “low”, respectively. The system is arranged s... | 08/22/2006 |
| 7095258 | Circuit arrangement for the provision of an output signal with adjustable flank pitch Circuitry is disclosed for controlling the slope of rising and falling edges of a signal. The circuitry includes a ramp signal generator that receives an input signal and that generates a trapezoidal signal based on the input signal, and a circuit array that receive... | 08/22/2006 |
| 7091743 | Data acknowledgment using impedance mismatching A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer bet... | 08/15/2006 |
