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| Number | Title | Issue Date |
| 8030968 | Staged predriver for high speed differential transmitter According to various embodiments, a differential transmitter includes a driver and a predriver. In various embodiments, the predriver may include pull-up transistors and pull-down transistors configured in various ways to produce a staged output signal during a pull... | 10/04/2011 |
| 7583105 | Pull-up circuit A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When t... | 09/01/2009 |
| 7362146 | Large supply range differential line driver A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may... | 04/22/2008 |
| 7355449 | High-speed serial data transmitter architecture Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pr... | 04/08/2008 |
| 7348811 | Equalizing transceiver with reduced parasitic capacitance A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a cor... | 03/25/2008 |
| 7327166 | Reference buffer with improved drift A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a ... | 02/05/2008 |
| 7301371 | Transmitter of a semiconductor device Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a con... | 11/27/2007 |
| 7295042 | Buffer A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull ope... | 11/13/2007 |
| 7285990 | High-precision buffer circuit A buffer circuit includes an input terminal operable to receive an input signal and an output terminal at which an output signal for the buffer circuit is provided. In the buffer circuit, three transistors at most provide signal currents. Two of the three transistor... | 10/23/2007 |
| 7274223 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 09/25/2007 |
| 7271626 | Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor ... | 09/18/2007 |
| 7253665 | Semiconductor device and driving method thereof The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current i... | 08/07/2007 |
| 7202710 | Apparatus and method for handling interdevice signaling An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting... | 04/10/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7161379 | Shunted current reduction One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current ... | 01/09/2007 |
| 7142017 | High-voltage-tolerant feedback coupled I/O buffer An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an... | 11/28/2006 |
| 7126389 | Method and apparatus for an output buffer with dynamic impedance control A method and apparatus for an output buffer with dynamic impedance control have been disclosed. ... | 10/24/2006 |
| 7123055 | Impedance-matched output driver circuits having coarse and fine tuning control Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein responsive to a ... | 10/17/2006 |
| 7116537 | Surge current prevention circuit and DC power supply A surge current prevention circuit and DC power supply for preventing surge current in various operation applications with a small circuit configuration. A power switch connects an external power supply and a load. A first PMOS transistor is connected to a constant ... | 10/03/2006 |
| 7095246 | Variable impedance output buffer An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), ... | 08/22/2006 |
| 7068074 | Voltage level translator circuit A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor d... | 06/27/2006 |
| 6998880 | Driver circuit The invention relates to a driver circuit with a circuit node (10), at least two first transistors (P1, P2), the load sections of which are switched in series and connect the circuit node (1... | 02/14/2006 |
| 6967512 | Multiphase-clock processing circuit and clock multiplying circuit In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1′ are connected i... | 11/22/2005 |
| 6919738 | Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the p... | 07/19/2005 |
| 6903581 | Output buffer for high and low voltage bus Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supp... | 06/07/2005 |
| 6885226 | Programmable dual-drive strength output buffer with a shared boot circuit An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive outpu... | 04/26/2005 |
| 6864090 | Method for testing the degradation of polymeric materials The present invention provides a novel method for monitoring the reaction kinetics of the biodegradable polymers, and the surface concentration of a drug in a polymer blend matrix. Detailed information on surface concentration, degradation rates, degradation kinetic... | 03/08/2005 |
| 6847238 | Output circuit and method for reducing simultaneous switching output skew An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a de... | 01/25/2005 |
| 6838915 | Input and output circuit of semiconductor device An input and output circuit of a semiconductor device is disclosed having an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series bet... | 01/04/2005 |
| 6831481 | Power-up and enable control circuits for interconnection arrays in programmable logic devices Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circu... | 12/14/2004 |
| 6819148 | CMOS comparator output stage and method A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal, (V7) on the gate of the pull-down transistor (MN) to turn on the pull-do... | 11/16/2004 |
| 6777976 | Interface circuit and semiconductor device with the same An output drive circuit is constructed by an output driving MOS transistor driving an output node in accordance with an internal read data, a termination controlling P-channel MOS transistor selectively rendered conductive in accordance with the internal read data w... | 08/17/2004 |
| 6573753 | Microcontroller input/output nodes with both programmable pull-up and pull-down resistive loads and programmable drive strength The present invention relates to an input/output node in an electronic device which comprises an input/output pin, a plurality of programmable pull-up resistors and a plurality of programmable pull-down resistors. Each of the pull-up and pull-down resisto... | 06/03/2003 |
| 6567877 | Automatically enabling terminator for internal SCSI buses with external SCSI bus expansion A computer system contains a small computer standard interface (SCSI) having a plurality of components to interface a plurality of external peripheral devices to the computer system in accordance with a SCSI specification. Within the computer system, the ... | 05/20/2003 |
| 6483340 | High integration-capable output buffer circuit unaffected by manufacturing process fluctuations or changes in use An output buffer circuit 1 comprises an output transistor section 10, a first and a second driving means 40, 50, and a first and a second switch circuits 60, 70. The output transistor section 10 comprises PMOS 11, 13, and NMOS 12, 14. Each source terminal... | 11/19/2002 |
| 6469565 | Duty cycle adaptive data output buffer The present invention relates to a duty cycle adaptive data output buffer of a semiconductor device in which the current driving power of the output buffer is adaptively varied with a duty cycle, to effectively improve noise margin at slow duty cycle. The... | 10/22/2002 |
| 6466074 | Low skew minimized clock splitter A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to ... | 10/15/2002 |
| 6462597 | Trip-point adjustment and delay chain circuits Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Di... | 10/08/2002 |
| 6326821 | Linearly-controlled resistive element apparatus Embodiments of the invention include an integrated circuit output buffer, with a pre-drive stage and an output driver stage, that provides linear performance independent of the load impedance. The output driver stage includes a pull-up resistor arrangemen... | 12/04/2001 |
| 6229355 | Switching device for suppressing a rush current A switching device includes a phase controlling circuit (801) which shifts and outputs a phase of a command signal, and a plurality of switching units (110) connected in parallel between a power supply (101) and a load (102). Each of the plurality of swit... | 05/08/2001 |
