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| Number | Title | Issue Date |
| 8179160 | Input-output (I/O) circuit supporting multiple I/O logic-level swings An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal... | 05/15/2012 |
| 8164360 | Semiconductor output circuit, external output signal generation method, and semiconductor device A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external outp... | 04/24/2012 |
| 8115515 | Radiation hardened differential output buffer A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the sam... | 02/14/2012 |
| 8063664 | Distributed supply current switch circuits for enabling individual power domains An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supp... | 11/22/2011 |
| 8054101 | Current source applicable to a controllable delay line and design method thereof A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with therm... | 11/08/2011 |
| 8044685 | Floating driving circuit A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is co... | 10/25/2011 |
| 8030967 | Method and apparatus involving a receiver with a selectable performance characteristic A circuit has a programmable mode control section, and a receiver section with first and second input terminals and an output terminal. The method and apparatus involve setting the mode control section to one of first and second states in response to user input, and... | 10/04/2011 |
| 8026741 | CMOS circuitry with mixed transistor parameters CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a... | 09/27/2011 |
| 8022729 | Signal driver circuit having adjustable output voltage for a high logic level output signal A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having ... | 09/20/2011 |
| 8022728 | Common-mode voltage controller A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for ... | 09/20/2011 |
| 8013633 | Thin film transistor logic A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circui... | 09/06/2011 |
| 8004312 | Fail safe I/O driver with pad feedback slew rate control Disclosed are a method, system and apparatus for an improved fail safe I/O driver with pad feedback slew rate control are disclosed. In one embodiment, a pad driver circuit includes a pad node, an NMOS component, a feedback capacitor between the pad node and a gate ... | 08/23/2011 |
| 7990178 | Driving circuit with impedence calibration A driving circuit includes at least a driving unit. The driving circuit includes a first bias component, a second bias component, and four metal-oxide-semiconductor (MOS) transistors. The first bias component has a first node coupled to a first reference voltage and... | 08/02/2011 |
| 7982501 | Low-power routing multiplexers Low-power routing multiplexers that reduce static and dynamic power consumption are provided. A variety of different techniques are used to reduce power consumption of the routing multiplexers without significantly increasing their size. For example, power consumpti... | 07/19/2011 |
| 7973562 | Universal sink/source I/O module for industrial controller An I/O module for an industrial controller provides single terminal outputs that may either sink or source current. This capability is provided through the use of dedicated sourcing and sinking transistors connected to the terminal and controlled by lockout logic en... | 07/05/2011 |
| 7969196 | Circuits and methods for buffering and communicating data signals Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, whe... | 06/28/2011 |
| 7969195 | Active biasing in metal oxide semiconductor (MOS) differential pairs Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and... | 06/28/2011 |
| 7956643 | Semiconductor device capable of switching operation modes and operation mode setting method therefor A semiconductor device according to the present invention includes: a first internal terminal; a second internal terminal; a first switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrical... | 06/07/2011 |
| 7944239 | System and method for providing live insertion System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection,... | 05/17/2011 |
| 7940085 | Inverter, method of operating the same and logic circuit comprising inverter Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor and a driving transistor, and at least one of the load transistor and the driving transistor may have a double gate s... | 05/10/2011 |
| 7924056 | Low voltage differential signalling driver A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect... | 04/12/2011 |
| 7919985 | Current-controlled CMOS circuits with inductive broadbanding Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each ci... | 04/05/2011 |
| 7919987 | Logic signal transmitting circuit A logic signal transmitting circuit includes a CMOS inverter, a first transistor switch and an inverter. The CMOS inverter includes a p-type transistor and an n-type transistor and is configured for inverting an input signal. The first transistor switch is connected... | 04/05/2011 |
| 7919986 | Power up biasing in a system having multiple input biasing modes This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the m... | 04/05/2011 |
| 7911233 | Semiconductor device including current source circuit The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage... | 03/22/2011 |
| 7902873 | Semiconductor chip and semiconductor device A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the... | 03/08/2011 |
| 7898294 | Pre-driver logic At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic ... | 03/01/2011 |
| 7893718 | High-speed multiplexer and semiconductor device including the same High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected ... | 02/22/2011 |
| 7880503 | Method of driving gate lines, gate line drive circuit for performing the method and display device having the gate line drive circuit A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is ou... | 02/01/2011 |
| 7868661 | Line driving circuit of semiconductor device Disclosed is a line driving circuit which includes two NMOS transistors in series between a supply voltage and a ground voltage. The output of the line driving circuit is applied to an interior circuit through a transmission line, and a repeater is used when the tra... | 01/11/2011 |
| 7859306 | Load driving circuit A load driving circuit comprising: a bias current circuit configured to generate a bias current having a current value corresponding to a level of a control signal; a control circuit configured to control the level of the control signal so that the bias current is i... | 12/28/2010 |
| 7852120 | Bi-directional buffer for open-drain or open-collector bus Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output no... | 12/14/2010 |
| 7847594 | Data output circuit of a semiconductor integrated circuit A data output circuit of a semiconductor integrated circuit includes a plurality of drivers configured to drive data output terminals to a logic level corresponding to levels of input data in response to driving control signals, and a control section configured to a... | 12/07/2010 |
| 7847593 | Semiconductor device, display device, and electronic device To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display devic... | 12/07/2010 |
| 7839174 | Mixed-voltage tolerant I/O buffer and output buffer circuit thereof An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second deter... | 11/23/2010 |
| 7825691 | Transmission circuit and related method A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit... | 11/02/2010 |
| 7825693 | Reduced duty cycle distortion using controlled body device A semiconductor chip comprising a reference circuit and a target circuit. The reference circuit comprises a first P-channel field effect transistor (PFET) and a first N-channel field effect transistor (NFET). A reference voltage is connected to gates of the first PF... | 11/02/2010 |
| 7825692 | Semiconductor memory device and output drive circuit thereof An apparatus for supplying current to a semiconductor memory device. A current supply circuit supplies current to an input/output (I/O) drive circuit responsive to a pattern of data input to the I/O drive circuit. The current supply circuit configured to supply curr... | 11/02/2010 |
| 7825694 | Differential output circuit A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS trans... | 11/02/2010 |
| 7821296 | Stacked buffers Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers tha... | 10/26/2010 |
