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| Number | Title | Issue Date |
| 8154320 | Voltage level shifter A level shifting circuit includes a string of diodes and an active load across which the control voltage is applied. A resistor is coupled across the lowermost diode to develop a switch control voltage. At low control voltage, the diode string allows no current to b... | 04/10/2012 |
| 8149017 | Low-voltage to high-voltage level translation using capacitive coupling A voltage level translator circuit has a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signa... | 04/03/2012 |
| 8120383 | Voltage level translation A virtual zero delay unidirectional high voltage logic to low voltage CMOS logic voltage level translator can be achieved using a capacitive voltage divider coupled with the standard protection diodes commonly incorporated in low side logic (e.g. Xilinx Spartan-3E F... | 02/21/2012 |
| 8018251 | Input/output interfacing with low power Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces o... | 09/13/2011 |
| 8008945 | Level-shift circuit A level-shift circuit converts a first voltage level into a second voltage level different from the first voltage level. The level-shift circuit includes a first high-side signal detection circuit, a second high-side signal detection circuit, a drive circuit and ele... | 08/30/2011 |
| 8006218 | Power mesh arrangement method utilized in an integrated circuit having multiple power domains The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second parti... | 08/23/2011 |
| 7999574 | Level conversion circuit and solid-state imaging device using the same According to one embodiment, a level conversion circuit includes an intermediate voltage generating portion to generate an intermediate voltage between a first voltage and a second voltage upon receiving the first voltage and the second voltage higher than the first... | 08/16/2011 |
| 7982498 | System and method for power domain isolation In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an outp... | 07/19/2011 |
| 7932747 | Circuit arrangement and method for shifting a voltage level A circuit arrangement for shifting a voltage level comprises a data-current converter (2) that is connected to a first connection (K1) and that has an input for feeding a digital input data signal (DIN), a first output for providing a current (I), and ... | 04/26/2011 |
| 7893715 | Arrangement and method for signal transmission between different voltage domains An arrangement and method for signal transmission between different voltage domains is disclosed. One embodiment provides a first signal processing unit receiving a first supply voltage. A second signal processing unit receives a second supply voltage, the first sup... | 02/22/2011 |
| 7880502 | Logic circuit A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element (1) having characteristics which maintain states, a first switching element (25) one end of which ... | 02/01/2011 |
| 7855575 | Wide voltage range level shifter with symmetrical switching Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a f... | 12/21/2010 |
| 7839171 | Digital level shifter and methods thereof A digital level shifter is disclosed that receives an input voltage from a first voltage domain, and provides an output voltage to a second voltage domain. The level shifter includes transistors configured in parallel with input transistors of the level shifter in o... | 11/23/2010 |
| 7839172 | Bidirectional buffer circuit and signal level conversion circuit A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first cont... | 11/23/2010 |
| 7816948 | Voltage translator A voltage translator having an input which receives an input signal and an output which provides a level shifted output signal includes a first inverter having an input coupled to receive the input signal, a second inverter having an input coupled to an output of th... | 10/19/2010 |
| 7812637 | Level shifter Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to ... | 10/12/2010 |
| 7804327 | Level shifters Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises fir... | 09/28/2010 |
| 7800407 | Multiple voltage mode pre-charging and selective level shifting To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to mainta... | 09/21/2010 |
| 7786760 | I/O buffer circuit An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the ... | 08/31/2010 |
| 7777524 | High voltage semiconductor device having shifters and method of fabricating the same Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low... | 08/17/2010 |
| 7755393 | Output driver for use in semiconductor device An output driver for use in a semiconductor device includes a first pre-drive unit, a second pre-drive unit, and a main drive unit. The first pre-drive unit generates a pull-up drive control signal based on a data signal. The pull-up drive control signal swings betw... | 07/13/2010 |
| 7733127 | Circuits and methods for communicating data between domains during voltage and frequency shifting When communicating data between different voltage and frequency domains, for example chiplets, in an integrated circuit, the data signals can be formatted to compensate for propagation delays and different operating frequencies between the domains, and the signaling... | 06/08/2010 |
| 7719312 | Apparatus for configuring I/O signal levels of interfacing logic circuits Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing inpu... | 05/18/2010 |
| 7710151 | Level shifter circuit A level shifter circuit includes a level shifter, an inverter, a first switch circuit and a second switch circuit. The level shifter includes a first transistor, a second transistor, a third transistor and a fourth transistor. The inverter receives an input signal a... | 05/04/2010 |
| 7710150 | Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a thres... | 05/04/2010 |
| 7649382 | Apparatus to reduce voltage swing for control signals The present invention provides for a device to reduce the voltage swing for control signals. An input signal with a maximum potential of DVDD and minimum potential of AVSS is level shifted to a maximum potential of AVDD and a minimum potential of AVDD-DVDD. A series... | 01/19/2010 |
| 7609090 | High speed level shifter Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS dev... | 10/27/2009 |
| 7598771 | Level shifter for gate driver A level shifter for a gate driver has a driving transistor, a reset transistor, a charge/discharge circuit, a threshold voltage detector, and a memory capacitor. An initial threshold voltage of the driving transistor is detected by the threshold voltage detector, an... | 10/06/2009 |
| 7589561 | Tolerant CMOS receiver A system includes a complementary metal oxide semiconductor (CMOS) receiver, a first transistor, and a tracking circuit. The tracking circuit receives an input voltage and a reference voltage and selectively biases the first transistor to one of the input voltage an... | 09/15/2009 |
| 7589560 | Apparatus for configuring I/O signal levels of interfacing logic circuits Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing inpu... | 09/15/2009 |
| 7579870 | Level shifter Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to ... | 08/25/2009 |
| 7545173 | Level shift delay equalization circuit and methodology Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon trans... | 06/09/2009 |
| 7443199 | Circuit arrangement for voltage selection, and method for operating a circuit arrangement for voltage selection The circuit arrangement includes a first and a second input to supply a first and a second supply voltage and also an output. The circuit arrangement includes a first transistor, which is connected between the first input and the output, and a second transistor, whi... | 10/28/2008 |
| 7443195 | Method of transparently reducing power consumption of a high-speed communication link A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to de... | 10/28/2008 |
| 7443200 | Capacitor-coupled level shifter with duty-cycle independence and supply referenced bias configuration A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the ... | 10/28/2008 |
| 7436212 | Interface circuit power reduction Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit... | 10/14/2008 |
| 7436213 | Level shifter In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which const... | 10/14/2008 |
| 7429875 | Low static current drain logic circuit A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output ... | 09/30/2008 |
| 7425845 | Semiconductor integrated circuit The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating... | 09/16/2008 |
| 7425860 | Level converting circuit A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a... | 09/16/2008 |
