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| Number | Title | Issue Date |
| 7372292 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 05/13/2008 |
| 7372303 | Semiconductor integrated circuit A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and ... | 05/13/2008 |
| 7352221 | Programmable amplifiers with positive and negative hysteresis Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer ... | 04/01/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7336100 | Single supply level converter A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input sign... | 02/26/2008 |
| 7330047 | Receiver circuit arrangement having an inverter circuit A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control tran... | 02/12/2008 |
| 7312509 | Digital temperature sensing device using temperature depending characteristic of contact resistance A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self... | 12/25/2007 |
| 7312635 | Integrated circuit provided with core unit and input and output unit A core unit implements a predetermined function. An I/O unit controls input from and output to the outside. The core unit and the I/O unit are subject to independent control for supply of power. When power is turned off in the core unit, a signal output from the I/O... | 12/25/2007 |
| 7288990 | Reference buffer with dynamic current control A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency o... | 10/30/2007 |
| 7274209 | Low voltage to high voltage signal level translator with improved performance A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third t... | 09/25/2007 |
| 7239178 | Circuit and method for CMOS voltage level translation A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second suppl... | 07/03/2007 |
| 7233170 | Programmable driver delay Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a ... | 06/19/2007 |
| 7230469 | Multi-level/single ended input level shifter circuit Methods are disclosed for translating or shifting a voltage level of a single ended input. More specifically, the present invention provides a method of translating or shifting a voltage level that doesn't require a complementary input or an additional power supply ... | 06/12/2007 |
| 7227402 | System and method for controlling input buffer biasing current A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a plurality of discrete biasing control signals. At least one input buffer is configured to adjust the bias... | 06/05/2007 |
| 7208999 | Step-down circuit with stabilized output voltage The present invention provides a semiconductor integrated circuit device equipped with a negative feedback amplifier circuit or a step-down circuit which realizes stabilization of an output voltage effectively in response to a variation in power supply voltage. A co... | 04/24/2007 |
| 7202699 | Voltage tolerant input buffer A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differ... | 04/10/2007 |
| 7190209 | Low-power high-performance integrated circuit and related methods An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on an... | 03/13/2007 |
| 7176722 | Low power high performance inverter circuit A low-power, high-performance inverter circuit comprises first and second inverter circuit portions. The first portion comprises a first inverter, including a first pull-up element and a first pull-down element, for inverting an input signal, a first switching eleme... | 02/13/2007 |
| 7170327 | System and method for data retention with reduced leakage current In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the ... | 01/30/2007 |
| 7167036 | Circuit for transforming signals varying between different voltages An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being grea... | 01/23/2007 |
| 7157941 | Differential switching circuit and digital-to-analog converter A differential switching circuit has a first transistor connected between a first output node and a common node and a second transistor connected between a second output node and the common node. A switching driver generates first and second driving signals in respo... | 01/02/2007 |
| 7142042 | Nulled error amplifier A multi-stage amplifier circuit that is arranged to minimize offset related errors in a reference circuit. The first stage circuit includes an array of amplifier circuits that receive feedback signals. The outputs of the first stage amplifier circuits are coupled to... | 11/28/2006 |
| 7131033 | Substrate configurable JTAG ID scheme A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response... | 10/31/2006 |
| 7123046 | Apparatus for adaptively adjusting a data receiver Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. T... | 10/17/2006 |
| 7119578 | Single supply level converter A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input sign... | 10/10/2006 |
| 7116307 | Level converter circuit, display device and portable terminal device This invention realizes reduction in consumption of DC current in a level converter circuit by setting level shifters in an operating state only when necessary in accordance with hierarchical control, in which an output pulse of a level shifter (311) that is ... | 10/03/2006 |
| 7109755 | Power delivery noise cancellation mechanism An integrated circuit is disclosed. The integrated circuit includes a power delivery network (PDN), a first voltage rail coupled to the PDN, an input/output (I/O) buffer coupled to the first voltage rail and a driver coupled to the I/O buffer. The driver transmits a... | 09/19/2006 |
| 7102545 | Simultaneous bidirectional input/output circuit Disclosed is a data detector for detecting data placed on a bi-directional data channel having two nodes. The data on the data channel is a combination of data placed on the data channel at both nodes. The data detector at the first node compares data received from ... | 09/05/2006 |
| 7098735 | Reference buffer with dynamic current control A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency o... | 08/29/2006 |
| 7064602 | Dynamic gain compensation and calibration Described are methods and circuits that reduce or eliminate the impact of power-supply fluctuations on circuit performance. IC dies include compensation circuitry that compares local power-supply voltages to relatively stable reference voltages, such as unloaded dis... | 06/20/2006 |
| 7038491 | Level shifter for wide range operation A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a progra... | 05/02/2006 |
| 7031889 | Method and apparatus for evaluating the design quality of network nodes A method and apparatus for evaluating the design quality of an integrated circuit design. The design to be evaluated comprises a plurality of static gates, such as, for example, NAND and NOR gates. The apparatus of the present invention comprises a computer configur... | 04/18/2006 |
| 7026859 | Control circuit for delay locked loop Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback cloc... | 04/11/2006 |
| 7005910 | Feed-forward circuit for reducing delay through an input buffer An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circu... | 02/28/2006 |
| 7002856 | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit... | 02/21/2006 |
| 6999739 | Stacked FET receiver method and apparatus A receiver method and apparatus is presented. Signals are received from a high-voltage environment to a low-voltage environment using low-voltage devices, such as low-voltage FETs. A reference stage (i.e., first stage) provides the reference point for an input signa... | 02/14/2006 |
| 6970022 | Controlled hysteresis comparator with rail-to-rail input Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator... | 11/29/2005 |
| 6970023 | Modulated transistor gate driver with planar pulse transformer Disclosed are methods and apparatus for isolating and driving a power supply or power amplifier circuit. The circuits and methods provide for using a modulated PWM input signal and its complement to drive one or more core-less transformers providing an isolated powe... | 11/29/2005 |
| 6970391 | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit... | 11/29/2005 |
| 6967501 | Impedance-matched output driver circuits having enhanced predriver control Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop containing differential amplifiers that set the resolution limit of the outpu... | 11/22/2005 |
