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| Number | Title | Issue Date |
| 8143916 | Level shift circuit, method for driving the same, and semiconductor circuit device having the same A level shift circuit includes a level shift section for receiving a low potential signal oscillating between a high potential and a ground potential and converting it into a high potential signal oscillating between the high potential and the ground potential, the ... | 03/27/2012 |
| 8143917 | Transceiver for controlling swing width of output voltage A transceiver for controlling a swing width of an output voltage includes a transmitter and a receiver for receiving an output voltage of a transmitter. The transmitter includes a first signal converter that outputs changed data generated by changing a voltage level... | 03/27/2012 |
| 8115514 | Pre-charged high-speed level shifters An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second p... | 02/14/2012 |
| 8111088 | Level shifter with balanced duty cycle A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted versio... | 02/07/2012 |
| 8085065 | Dual loop level shifter A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, inte... | 12/27/2011 |
| 8049532 | Level shifter circuit with a thin gate oxide transistor A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connecte... | 11/01/2011 |
| 7999573 | Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where ... | 08/16/2011 |
| 7994820 | Level shifter with embedded logic and low minimum voltage In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different pow... | 08/09/2011 |
| 7994819 | Level-shifter circuit One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an in... | 08/09/2011 |
| 7973560 | Level shifter A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude le... | 07/05/2011 |
| 7956642 | Level shifter having low duty cycle distortion A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is p... | 06/07/2011 |
| 7952388 | Semiconductor device A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second vo... | 05/31/2011 |
| 7952389 | Level shift circuit A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2 | 05/31/2011 |
| 7928766 | Semi-buffered auto-direction-sensing voltage translator In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-dra... | 04/19/2011 |
| 7902870 | High speed level shifter circuit in advanced CMOS technology A level shifter circuit for shifting from a first voltage level technology (such as 0.9 volt) to a second level voltage technology (such as 3.3 volt) with increased switching speed. The increased speed is achieved by adding a boost circuit to the pull-up transistors... | 03/08/2011 |
| 7898292 | Level converter A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the... | 03/01/2011 |
| 7893714 | High voltage analog multiplex switch integrated circuit architecture An integrated circuit high voltage analog switch has digital logic-level control interface circuit. A level translator is coupled to the digital logic-level control interface circuit. A plurality of output multi-channel high voltage switches is coupled to the level ... | 02/22/2011 |
| 7888967 | Level translator circuit A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating fr... | 02/15/2011 |
| 7884643 | Low leakage voltage level shifting circuit A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors ... | 02/08/2011 |
| 7884644 | Techniques for adjusting level shifted signals A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at contr... | 02/08/2011 |
| 7880501 | Integrated circuit devices having level shifting circuits therein Level shifting circuits generate multiple tracking signals that are in-phase with an input signal, but are also level-shifted with wider voltage swings relative to the input signal. These input tracking signals are provided as separate inputs to an inverter having a... | 02/01/2011 |
| 7880500 | Logical signal voltage converter A circuit for converting a lower voltage logical signal to a higher voltage. The circuit comprises a current mirror structure having first and second branches, each comprising at least a first transistor of a first kind, an input transistor of a second kind, and a s... | 02/01/2011 |
| 7872498 | Current mode circuitry to modulate a common mode voltage In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a firs... | 01/18/2011 |
| 7868658 | Level shifter circuits and methods for maintaining duty cycle A circuit comprises first and second buffers, and an output buffer. The first buffer receives an input signal and provides a first buffer output signal on a first lead. The second buffer receives the input signal and provides a second buffer output signal on a secon... | 01/11/2011 |
| 7855574 | Programmable multiple supply regions with switched pass gate level converters A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is s... | 12/21/2010 |
| 7852118 | High speed conditional back bias virtual ground restoration circuit A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more l... | 12/14/2010 |
| 7847591 | Low jitter CMOS to CML converter The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input t... | 12/07/2010 |
| 7847590 | Level shifter including cascode sets A device for shifting voltage levels includes an input stage, an output stage and multiple cascode sets connected between the input stage and the output stage. The input stage includes input transistors connected to a first voltage and an input for receiving an inpu... | 12/07/2010 |
| 7847592 | Buffer circuit of semiconductor memory apparatus A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation... | 12/07/2010 |
| 7843221 | Semiconductor device, display panel and electronic equipment The present invention provides a semiconductor device having a buffer circuit formed on an insulating substrate using single-channel type thin film transistors, wherein the buffer circuit has an output stage which including first and second thin film transistors con... | 11/30/2010 |
| 7839170 | Low power single rail input voltage level shifter One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from a low voltage domain to a high voltage domain, where VDDH is the supply voltage of the high voltage domain and VDDL is the supply voltage of the low voltage... | 11/23/2010 |
| 7834661 | Ultra-low-power level shifter, voltage transform circuit and RFID tag including the same A level shifter increase a voltage level of an output signal with relatively lower power consumption by adopting current-starved configuration. The level shifter includes an input unit and a driving unit. The input unit includes a current-starved inverter configured... | 11/16/2010 |
| 7834662 | Level shifter with embedded logic and low minimum voltage In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different pow... | 11/16/2010 |
| 7830175 | Low power single-rail-input voltage level shifter An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail ... | 11/09/2010 |
| 7804326 | Voltage level shifter A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a se... | 09/28/2010 |
| 7795916 | Level shift circuit A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2 | 09/14/2010 |
| 7791371 | Level shift circuit and power semiconductor device A level shift circuit includes a drive transistor, a first PMOS transistor, and first and second clamp transistors of PMOS type. The drive transistor, which drives the gate of the high-side NMOS transistor in a power semiconductor device, has a source-drain path cou... | 09/07/2010 |
| 7786759 | Bidirectional signal interface and related system and method An embodiment of a bidirectional signal interface includes first and second nodes and first and second translating circuits. The first and second nodes are respectively operable to receive a first logic signal and a second logic signal. The first translating circuit... | 08/31/2010 |
| 7777522 | Clocked single power supply level shifter First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes ref... | 08/17/2010 |
| 7777521 | Method and circuitry to translate a differential logic signal to a CMOS logic signal Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is incl... | 08/17/2010 |
