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| Number | Title | Issue Date |
| 7969189 | Method and system for improved phase noise in a BiCMOS clock driver System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to t... | 06/28/2011 |
| 7928765 | Tuning high-side and low-side CMOS data-paths in CML-to-CMOS signal converter Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic... | 04/19/2011 |
| 7688110 | System for providing a complementary metal-oxide semiconductor (CMOS) emitter coupled logic (ECL) equivalent input/output (I/O) circuit A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/... | 03/30/2010 |
| 7646219 | Translator circuit having internal positive feedback An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141( | 01/12/2010 |
| 7595660 | Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals... | 09/29/2009 |
| 7372298 | Chip with adjustable pinout function and method thereof A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circu... | 05/13/2008 |
| 7373531 | Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus A power consumption control device for detecting output of a pulse signal from an output terminal of an oscillator as an operation monitoring target and outputting a power consumption reduction signal when the pulse signal is not detected in a predetermined period o... | 05/13/2008 |
| 7358810 | Buffer amplifier A buffer amplifier, which includes a first differential signal amplifier including first and second NMOSFETs (N-type metal-oxide semiconductor field-effect transistors) amplifying differential input signals; a second differential signal amplifier including first and... | 04/15/2008 |
| 7352229 | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of dif... | 04/01/2008 |
| 7342439 | Current bias circuit and current bias start-up circuit thereof A current bias circuit and a current bias start-up circuit thereof are disclosed. The bias start-up circuit supplies a compensation current to the bias circuit to compensate the leakage current of the current bias circuit during activation and turns off the compensa... | 03/11/2008 |
| 7327164 | Interface circuit An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predeter... | 02/05/2008 |
| 7301370 | High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is incl... | 11/27/2007 |
| 7274256 | Input amplifier stage in the AB class having a controlled bias current The invention relates to an input amplifier stage, in AB class, having a controlled bias current and comprising a differential cell, inserted between a first supply voltage reference and a second voltage reference, having a differential pair of input transistors rec... | 09/25/2007 |
| 7274209 | Low voltage to high voltage signal level translator with improved performance A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third t... | 09/25/2007 |
| 7248075 | Level shifter with low leakage current A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signa... | 07/24/2007 |
| 7224202 | Self-biased high voltage level shifter A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to pro... | 05/29/2007 |
| 7218174 | Delay circuit and method therefor In one embodiment, a delay circuit is formed to use cascode coupled transistors to receive signals from a differential pair and increase the propagation through the delay circuit. ... | 05/15/2007 |
| 7206876 | Input/output interface of an integrated circuit device An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each... | 04/17/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7176720 | Low duty cycle distortion differential to CMOS translator Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be tra... | 02/13/2007 |
| 7129750 | CMOS to PECL voltage level converter A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and proc... | 10/31/2006 |
| 7126382 | Lower power high speed design in BiCMOS processes A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-... | 10/24/2006 |
| 7106104 | Integrated line driver The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimize... | 09/12/2006 |
| 7099786 | Signaling accommodation A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensat... | 08/29/2006 |
| 7099395 | Reducing coupled noise in pseudo-differential signaling systems A pseudo-differential signaling system uses a plurality of signal lines and a single, common reference voltage. Signal line voltages are interpreted only in comparison to the reference line voltage. Within a receiving circuit, the reference line is buffered prior to... | 08/29/2006 |
| 7083984 | Hybrid phthalocyanine derivatives and their uses Water soluble hybrid phthalocyanine derivatives useful in competitive and noncompetitive assays immunoassays, nucleic acid and assays are disclosed and claimed having (1) at least one donor subunit with a desired excitation peak; and (2) at least one acceptor subuni... | 08/01/2006 |
| 7084694 | Switching circuit for switching constant current source using MOS transistor A basic switching circuit combines CMOS and bipolar technique on SiGe basis and operates at a low operating voltage of only slightly more than 2V. To achieve this low operating voltage, switching operation of the circuit is effected by switching a constant current s... | 08/01/2006 |
| 7068073 | Circuit for switching one or more HVD transceivers The output of an open-collector comparator and a programmable logic device are connected to a high voltage differential device. In conjunction with the comparator output, the programmable logic device controls the diffsense prime signal sent to the high voltage diff... | 06/27/2006 |
| 7064598 | Radio frequency CMOS buffer circuit and method A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode couple... | 06/20/2006 |
| 7064602 | Dynamic gain compensation and calibration Described are methods and circuits that reduce or eliminate the impact of power-supply fluctuations on circuit performance. IC dies include compensation circuitry that compares local power-supply voltages to relatively stable reference voltages, such as unloaded dis... | 06/20/2006 |
| 7053671 | Low-jitter differential-to-single-ended data conversion circuits Circuitry is provided for converting differential digital data to single-ended digital data. Differential data signals have complementary pairs of signals that are referenced to each other. Single-ended signals are referenced to ground. The circuitry can be used on ... | 05/30/2006 |
| 7046072 | Commutating phase selector A phase selector for selecting a differential output can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the ... | 05/16/2006 |
| 7046567 | Sense amplifying circuit and bit comparator with the sense amplifying circuit A sense amplifying circuit and a bit comparator having the sense amplifying circuit. The sense amplifying circuit may include a selecting unit, a sensing unit, a latching unit, an output unit, and a switching unit. The selecting unit may select one pair from a first... | 05/16/2006 |
| 6956400 | Converter from ECL to CMOS and network element for transmitting signals The invention relates to a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2 | 10/18/2005 |
| 6930515 | Level shifting and level shifting amplifier circuits Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are... | 08/16/2005 |
| 6924667 | Level shifting and level-shifting amplifier circuits Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are... | 08/02/2005 |
| 6882178 | Input circuit An input circuit comprises an input terminal for receiving an input signal, an output terminal for outputting an output signal, a node connected to the input terminal, a terminating resistor connected between the node and a ground, a potential shift element connecte... | 04/19/2005 |
| 6847233 | Emitter coupled logic circuit with a data reload function An emitter coupled logic circuit with a data reload function is disclosed. The emitter coupled logic (ECL) circuit includes first and second in series transistors consisting of bipolar junction transistors (BJTs) and field effect transistors (FETs), respectively. Th... | 01/25/2005 |
| 6593774 | CMOS-interfaceable ECL integrated circuit with tri-state and adjustable amplitude outputs An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emi... | 07/15/2003 |
| 6535017 | CMOS ECL input buffer A CMOS ECL input buffer buffers signals from an ECL circuit to a CMOS circuit. The CMOS ECL input buffer has a CMOS differential amplifier. A CMOS input circuit is coupled between a buffer input that receives the ECL circuit and a first input of the CMOS ... | 03/18/2003 |
