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| Number | Title | Issue Date |
| 7382172 | Level shift circuit and method for the same The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operati... | 06/03/2008 |
| 7373090 | Modulator driver circuit with selectable on-chip termination A method and apparatus to accommodate differing output loads without sacrificing impedance matching in an optical modulator driver. ... | 05/13/2008 |
| 7327620 | Differential input buffer for receiving signals relevant to low power Disclosed herein are exemplary embodiments of an improved differential input buffer for receiving low power signals and associated methods. The disclosed buffer circuit comprises at least one differential amplifier for receiving as inputs an enable signal (e.g., a c... | 02/05/2008 |
| 7248075 | Level shifter with low leakage current A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signa... | 07/24/2007 |
| 7215173 | Low-swing level shifter In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted ver... | 05/08/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7183832 | Level shifter with boost and attenuation programming A level shifter circuit includes a bias module that receives a first voltage value, that generates a second voltage value when an operational frequency of the level shifter circuit is less than a threshold, and that generates a third voltage value when the operation... | 02/27/2007 |
| 7176720 | Low duty cycle distortion differential to CMOS translator Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be tra... | 02/13/2007 |
| 7138822 | Integrated circuit and method of improving signal integrity An integrated circuit comprising a first output stage circuit and a second output stage circuit that share common input terminals and an output terminal of the first and second output stage circuits being selectably coupled between the input terminals and the output... | 11/21/2006 |
| 7109779 | Semiconductor integrated circuit and a burn-in method thereof A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circu... | 09/19/2006 |
| 7088142 | Semiconductor integrated circuit and level conversion circuit A semiconductor integrated circuit for decreasing level fluctuation in an output signal of a level conversion circuit. The level conversion circuit has a pair of series-connected transistors including a first MOS transistor and a second MOS transistor and a further ... | 08/08/2006 |
| 7084694 | Switching circuit for switching constant current source using MOS transistor A basic switching circuit combines CMOS and bipolar technique on SiGe basis and operates at a low operating voltage of only slightly more than 2V. To achieve this low operating voltage, switching operation of the circuit is effected by switching a constant current s... | 08/01/2006 |
| 7068090 | Amplifier circuit An amplifier circuit includes a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit includes a PMOS transist... | 06/27/2006 |
| 6998881 | Semiconductor integrated circuit device In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a b... | 02/14/2006 |
| 6518789 | Circuit configuration for converting logic levels The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having ... | 02/11/2003 |
| 6236233 | Method and system for translating TTL off-chip drive for integrated circuit with negative substrate bias The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately a... | 05/22/2001 |
| 6211699 | High performance CML to CMOS converter The present invention is a CML to CMOS converter which includes a bipolar input stage, a current source/current sink stage, and an output stage. The converter is able to transfer a CML input voltage differential to a CMOS compatible voltage having constan... | 04/03/2001 |
| 6043678 | Input circuit According to the present invention, an input circuit is provided comprising: an input terminal; a first power source terminal; a second power source terminal; a first bipolar transistor; a second bipolar transistor; a first electric current cut off member... | 03/28/2000 |
| 6040710 | CML-CMOS conversion circuit A CML-CMOS conversion circuit according to this invention includes: a differential circuit in which resistance is connected as load; a first current mirror circuit made up from an n-channel MOS transistor connected to one output of the differential circui... | 03/21/2000 |
| 5966032 | BiCMOS transceiver (driver and receiver) for gigahertz operation Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported.... | 10/12/1999 |
| 5920729 | Apparatus for providing pair of complementary outputs with first and subcircuits to convert non-complementary and complementary inputs to first and second pair of complementary output A write driver, having a pair of inputs for receiving write data signals, includes a TTL buffer circuit connected to one input and a PECL buffer circuit connected to both inputs. A detector, responsive to a voltage at one of the inputs, selectively operat... | 07/06/1999 |
| 5900745 | Semiconductor device including input buffer circuit capable of amplifying input signal with low amplitude in high speed and under low current consumption A semiconductor device is arranged by a push-pull circuit 1 for shifting a first center potential of an amplitude of an input signal to a second center potential, and for outputting first and seconc complimentary signals P1, P2 having said second center p... | 05/04/1999 |
| 5696715 | Semiconductor memory device having bipolar and field effect transistors and an improved coupling arrangement for logic units or logic blocks A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. B... | 12/09/1997 |
| 5682108 | High speed level translator A high speed level translator is disclosed in which an ECL differential input signal is applied to a differential input amplifier, amplified, and converted to a single ended intermediate signal. An inverter circuit receives the intermediate signal and out... | 10/28/1997 |
| 5561388 | Semiconductor device having CMOS circuit and bipolar circuit mixed In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and a second power supply voltage, and the CMOS circuit and a level conversion circuit between a CMOS leve... | 10/01/1996 |
| 5512847 | BiCMOS tri-state output driver In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bi... | 04/30/1996 |
| 5450026 | Current mode driver for differential bus The current mode bus driver which is disclosed couples input digital signals to a bus which is normally biased with a voltage difference representing one binary type. The current mode bus driver responds to input digital signals of the other binary type b... | 09/12/1995 |
| 5446400 | GTL compatible BICMOS input stage A BICMOS input stage includes a level shifting stage (35) and a level converter/buffer circuit (60). The input stage receives a single-ended GTL level input signal and a reference voltage, and in response, provides differential BICMOS level output signals... | 08/29/1995 |
| 5412262 | Semiconductor integrated circuit device having plurality of supply potential lines connected thereto, and system employing the same In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the nu... | 05/02/1995 |
| 5362997 | BiCMOS output driver A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up circuit for pulling high the output of the Output Driver and a pull-down circuit for pulling low the output of the Output Driver. The first pull-up means includes ... | 11/08/1994 |
| 5359553 | Low power ECL/MOS level converting circuit and memory device and method of converting a signal level A level converting circuit comprises first and second complementary metal oxide semiconductor (CMOS) inverter circuits, and first and second N-Channel metal oxide semiconductor (NMOS) transistors. The first CMOS inverter circuit and the first transistor a... | 10/25/1994 |
| 5343093 | Self referencing MOS to ECL level conversion circuit A MOS to ECL level conversion circuit is disclosed which comprises transistors forming a differential pair connected to a current source. One of the transistors is configured as a diode and is self-referencing in that it supplies its own reference voltage... | 08/30/1994 |
| 5315179 | BICMOS level converter circuit A BICMOS level converter (60) for use at lower power supply voltages includes an input buffer (20) for receiving an ECL level input signal and providing level shifted buffered signals referenced to VSS, a differential amplifier (61), a clamping... | 05/24/1994 |
| 5304869 | BiCMOS digital amplifier A BiCMOS circuit for amplifying the difference voltage between two input voltage signals. The BiCMOS circuit of the present invention includes two bipolar junction transistor which receive the two input voltage signals and each drive a cascode-connected P... | 04/19/1994 |
| 5276364 | BiCMOS bus interface output driver compatible with a mixed voltage system environment A low voltage BiCMOS output driver that is operable in a mixed voltage signal environment is provided which comprises a pull-up transistor and blocking circuitry operable to block current flow from the mixed voltage signal environment through the BiCMOS o... | 01/04/1994 |
| 5216298 | ECL input buffer for BiCMOS An ECL buffer circuit includes an input portion for receiving an input signal at an ECL level, a current switch portion and an output portion. The input portion includes a bipolar transistor (Q1), a level-shift diode (D1) and a constant current source (CS... | 06/01/1993 |
| 5077492 | BiCMOS circuitry having a combination CMOS gate and a bipolar transistor A level shift element is contained in a through current path of a CMOS gate of a BiCMOS circuit. The level shift element limits an amplitude of an input signal to the BiCMOS circuit. The limited amplitude of the input signal controls the impact ionization... | 12/31/1991 |
| 5030856 | Receiver and level converter circuit with dual feedback A receiver and level converter circuit is disclosed which may be used, for example, in converting low-level logic or other signals to high-level signals. In one embodiment, the circuit includes a differential amplifier having two feedback loops to provide... | 07/09/1991 |
| 4999523 | BICMOS logic gate with higher pull-up voltage A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor ... | 03/12/1991 |
| 4982117 | Address transition detector circuit An address transition detector circuit detects a transition of an address signal. The address transition detector circuit has a first circuit part which includes two field effect transistors which are coupled in series and simultaneously turn ON when an a... | 01/01/1991 |