Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8022726 | Multi-level signaling A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states ... | 09/20/2011 |
| 7965103 | Quad to binary converter with directly connected and coupled outputs Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 06/21/2011 |
| 7868657 | High voltage logic circuits High voltage logic circuits that can handle digital input and output signals having a larger voltage range are described. In an exemplary design, a high voltage logic circuit includes an input stage, a second stage, and an output stage. The input stage receives at l... | 01/11/2011 |
| 7795915 | Multi-level signaling A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states ... | 09/14/2010 |
| 7782089 | Multi-state latches from n-state reversible inverters N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversin... | 08/24/2010 |
| 7768305 | Quad state to two state interface circuitry with clock input Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 08/03/2010 |
| 7755391 | Three-valued logic function circuit There is provided a three-valued logic function circuit capable of remarkably reducing the kinds of basic circuits necessary for realizing all 33^2=19683 kinds of two-variable three-valued logic function circuits, remarkably reducing asymmetry of the swit... | 07/13/2010 |
| 7696785 | Implementing logic functions with non-magnitude based physical phenomena An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a... | 04/13/2010 |
| 7656196 | Multi-state latches from n-state reversible inverters N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversin... | 02/02/2010 |
| 7548092 | Implementing logic functions with non-magnitude based physical phenomena An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a... | 06/16/2009 |
| 7541836 | Binary boolean output on input with more than two states Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 06/02/2009 |
| 7403036 | Interface circuit As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control ena... | 07/22/2008 |
| 7397690 | Multi-valued digital information retaining elements and memory devices Discussed are models and methods to create stable binary and non-binary sequential devices including one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input informati... | 07/08/2008 |
| 7385422 | Tri-state output logic with zero quiescent current by one input control A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage ... | 06/10/2008 |
| 7373569 | Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also com... | 05/13/2008 |
| 7355444 | Single and composite binary and multi-valued logic functions from gates and inverters Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input ... | 04/08/2008 |
| 7327162 | Operations with logical states from a four voltage level signal Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 02/05/2008 |
| 7218144 | Single and composite binary and multi-valued logic functions from gates and inverters Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input ... | 05/15/2007 |
| 7199611 | System to temporarily modify an output waveform Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provi... | 04/03/2007 |
| 7187673 | Technique for creating a machine to route non-packetized digital signals using distributed RAM A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The mem... | 03/06/2007 |
| 7183792 | Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mod... | 02/27/2007 |
| 7167109 | Hybrid fractional-bit systems The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, result... | 01/23/2007 |
| 7157939 | Quad state memory with converter feedback, transmission, and clock circuitry Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 01/02/2007 |
| 7142132 | Methods and systems for multi-state switching using at least one ternary input and at least one discrete input Systems, methods and devices are described for placing a controlled device into a desired operating state in response to the position of a multi-position actuator. Two or more switch contacts provide input signals representative of the position of the actuator. Cont... | 11/28/2006 |
| 7123045 | Semiconductor integrated circuit device When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released. ... | 10/17/2006 |
| 7098833 | Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid... | 08/29/2006 |
| 7071849 | Fractional-Bit Systems The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, result... | 07/04/2006 |
| 7053655 | Multi-level driver stage An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of ΔV, includes a plurality of field effect transistors for driving the output by supplying or removing a current to or from the output... | 05/30/2006 |
| 7003510 | Table module compiler equivalent to ROM A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising su... | 02/21/2006 |
| 6963225 | Quad state logic design methods, circuits, and systems Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integr... | 11/08/2005 |
| 6930513 | Simultaneous bi-directional signal transmission system and semiconductor device therefor A simultaneous bi-directional signal transmission system includes a first semiconductor device, a second semiconductor device, and one or more transmission lines. The first semiconductor device includes a first output MUX which receives first binary data and convert... | 08/16/2005 |
| 6888765 | Integrated circuit and method for testing same using single pin to control test mode and normal mode operation An integrated circuit including operational circuitry operable in response to at least one control signal asserted to an external node from an external source, and test circuitry coupled to the external node and the operational circuitry. In response to data asserte... | 05/03/2005 |
| 6842044 | Glitch-free receivers for bi-directional, simultaneous data bus A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay un... | 01/11/2005 |
| 6794899 | On chip method and apparatus for transmission of multiple bits using quantized voltage levels Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four l... | 09/21/2004 |
| 6714045 | Static transmission of FAST14 logic 1-of-N signals A static output signal is generated using a static storage element (104) and transmitted to a NDL gate (110) over a transmission path (112) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriat... | 03/30/2004 |
| 6700406 | Multi-valued logical circuit with less latch-up This three-valued inverter includes first and second P-channel MOS transistors connected in series between a line of a first power supply potential and an output node, and each having a gate receiving a first signal; third and fourth P-channel MOS transis... | 03/02/2004 |
| 6636076 | Quad state logic design methods, circuits, and systems Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower p... | 10/21/2003 |
| 6486697 | Line reflection reduction with energy-recovery driver A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level du... | 11/26/2002 |
| 6392445 | Decoder element for producing an output signal having three different potentials The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of th... | 05/21/2002 |
| 6377073 | Structure and method for reduction of power consumption in integrated circuit logic A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single threshold. A significant portion of an IC's power dissipat... | 04/23/2002 |
