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| Number | Title | Issue Date |
| 6246264 | Circuit for generating output signals as a function of input signals An output driver circuit of a clocked integrated semiconductor memory of the DRAM type is driven by a circuit for generating an output signal as a function of two input signals. A validity signal, which is supplied to the circuit, ensures that the data to... | 06/12/2001 |
| 6236235 | Output circuit In an output circuit having an input/output terminal, first and second p-channel MOS transistors are serially connected between a power supply and the input/output terminal. An enable signal and an input signal are supplied to an NAND circuit. The gate of... | 05/22/2001 |
| 6222388 | Low voltage differential driver with multiple drive strengths The first pulse problem for a low-voltage differential SCSI bus driver is remedied by supplying greater power for a first pulse of a bus line after a steady state condition. Activity detection circuitry detects when a signal has remained in a steady state... | 04/24/2001 |
| 6222397 | Output circuit with switching function An output circuit having a function of two or more external interfaces is disclosed. The disclosed output circuit has an input circuit generating an internal input signal in response to an external input signal, an output circuit including a pMOS transist... | 04/24/2001 |
| 6211702 | Input circuit An input circuit is provided with a gate with an input end thereof connected to an input terminal to which an external signal is input, the gate allows or prohibits the output of the external signal in accordance with a control signal. The input circuit a... | 04/03/2001 |
| 6184700 | Fail safe buffer capable of operating with a mixed voltage core A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in ... | 02/06/2001 |
| 6177808 | Integration of bidirectional switches with programmable logic In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic... | 01/23/2001 |
| 6172522 | Slew rate controlled predriver circuit A digital CMOS predriver circuit pulls an output node up and down with accurately controlled rise and fall times in the threshold region. Resistors independently set rise and fall slew rates while additional CMOS devices initially charge and discharge the... | 01/09/2001 |
| 6172527 | Output circuit capable of reducing feedthrough current Signals inputted from nodes N2 and N4 to output circuit 100 are respectively transmitted to clocked inverters 31 and 32. Clocked inverter 31 is activated when node N4 is H level while clocked inverter 32 is activated when node N2 is L level. Output signal... | 01/09/2001 |
| 6169420 | Output buffer An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an externa... | 01/02/2001 |
| 6166561 | Method and apparatus for protecting off chip driver circuitry employing a split rail power supply OCD circuitry is provided for an integrated circuit having a split rail power supply providing a first and a second voltage. The OCD circuitry comprises a tristate logic circuit adapted to control the OCD and a detection circuit coupled to the tristate lo... | 12/26/2000 |
| 6163169 | CMOS tri-state control circuit for a bidirectional I/O with slew rate control A digital circuit pulls up an output node using an NFET device. The digital circuit is part of a CMOS predriver having balanced delays for coming out of tristate mode and for data mode operation. The predriver has size and speed capability advantages and ... | 12/19/2000 |
| 6154056 | Tri-stating address input circuit An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input sta... | 11/28/2000 |
| 6154058 | Output buffer An output buffer includes a p-channel transistor, and first and second n-channel transistors. The p-channel transistor has one of a source and drain which is connected to power supply and the other which is connected to an output node connected to an outp... | 11/28/2000 |
| 6150843 | Five volt tolerant I/O buffer A 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage, for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current ... | 11/21/2000 |
| 6150844 | High voltage tolerance output stage An output stage for electronic circuits with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair comprising a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor. The transis... | 11/21/2000 |
| 6137310 | Serial switch driver architecture for automatic test equipment A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for coupling to the pin. A first switching unit couples to the out... | 10/24/2000 |
| 6121795 | Low-voltage input/output circuit with high voltage tolerance An input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal of an integrated circuit device, such as a Programmable Logic Device (PLD). The I/O circuit includes pull-up and pull-down transistors for gen... | 09/19/2000 |
| 6118303 | Integrated circuit I/O buffer having pass gate protection with RC delay An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad term... | 09/12/2000 |
| 6118301 | High voltage tolerant and compliant driver circuit An input/output driver circuit which provides a buffer interface between a functional digital circuit and a common bus for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins, by usin... | 09/12/2000 |
| 6118305 | Semiconductor integrated circuit capable of preventing breakdown of a gate oxide film The present invention provides a semiconductor integrated circuit comprising a plurality of logic circuits, each of which has at least a first field effect transistor with a first gate connected to a high voltage line and at least a second field effect tr... | 09/12/2000 |
| 6114884 | Driver circuit providing early release and quick bus turn-around In a system of plural bus driver circuits connected to a shared bus line, each of the driver circuits has combinatorial logic responsive, driving a final clock cycle for an active driver, to the difference between the data input and output of a tri-state ... | 09/05/2000 |
| 6111426 | Logic signal output buffer circuit An output buffer circuit for logic signals produces an output logic signal from an input logic signal. It comprises a storage circuit capable of storing the logic state of the input signal and an output stage to produce the output signal as a function of ... | 08/29/2000 |
| 6111432 | Symmetric adapter unit for switching a logic signal A symmetric adapter unit for switching a logic signal implemented in CMOS technology that includes a control module for transmission and non-transmission of the logic signal, receiving this logic signal and a control logic signal to deliver a first and a ... | 08/29/2000 |
| 6107828 | Programmable buffer circuit and a mask ROM device having the same A programmable buffer circuit comprises a logical gate circuit having a second input terminal, a third input terminal and a first output terminal, and a first input terminal. The second input terminal is connected to the first input terminal. Further, a s... | 08/22/2000 |
| 6097208 | Signal-transfer system and semiconductor device for high-speed data transfer A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor. The signal-transfer system includes a line having an equalized characteristic impedance Z0, and an output circuit having an output turn-on ... | 08/01/2000 |
| 6091260 | Integrated circuit output buffers having low propagation delay and improved noise characteristics Integrated circuit output buffers include first and second pull-down switches and a preferred pull-down control circuit which utilizes a preferred feedback technique to facilitate a reduction in simultaneous-switching noise during pull-down operations and... | 07/18/2000 |
| 6087870 | Output circuit which switches an output state in accordance with a timing signal and a delay signal of the timing signal An output circuit according to the present invention is provided with a delay circuit for delaying an enable control signal by a predetermined period td and an output means capable of controlling the output state in either an enable or a disable state, wh... | 07/11/2000 |
| 6072728 | Data output buffer For use in a semiconductor circuit device, a uniquely-arranged tri-state output buffer responds to a control signal generated in the semiconductor circuit device and a below-ground voltage level at an output terminal to prevent wasted drain current and su... | 06/06/2000 |
| 6072333 | Tristate output circuit The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amp... | 06/06/2000 |
| 6066958 | Semiconductor integrated circuit There are provided an output buffer circuit and an input/output buffer circuit each including pre-driver circuit and main driver circuit divided to a plurality of stages and a delay circuit and enabling operations of the main driver circuit successively w... | 05/23/2000 |
| 6064227 | Output buffer circuit having low breakdown voltage In an output buffer circuit, a logic circuit generates first and second data signals each having a voltage level between a low voltage and a first high voltage. A level shift circuit receives the first data signal and generates a third data signal having ... | 05/16/2000 |
| 6060906 | Bidirectional buffer with active pull-up/latch circuit for mixed-voltage applications In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VDD, to a second device having a second voltage, such as VCC, through a terminal pad. The buffer includ... | 05/09/2000 |
| 6043680 | 5V tolerant I/O buffer A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transist... | 03/28/2000 |
| 6040714 | Method for providing two modes of I/O pad termination The present invention provides a method of providing two different modes of operation for an output driver on an integrated circuit. A first mode provides an open drain driver, such as an enhanced GTL+ driver, for high-speed data transmission. A second mo... | 03/21/2000 |
| 6037802 | Tristate buffer having a bipolar transistor A tristate buffer comprises an output block having a pair of NPN bipolar transistor and nMOS transistor between the source line and ground line and connected to each other at the output terminal of the tristate buffer. The tristate buffer has a base poten... | 03/14/2000 |
| 6034553 | Bus switch having both p- and n-channel transistors for constant impedance using isolation circuit for live-insertion when powered down A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the n... | 03/07/2000 |
| 6031394 | Low voltage CMOS circuit for on/off chip drive at high voltage A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages ... | 02/29/2000 |
| 6020762 | Digital voltage translator and its method of operation A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and output a signal transitioning within a higher voltage range. Circuitry is provided to ensure pr... | 02/01/2000 |
| 6011409 | Input/output buffer capable of accepting an input logic signal higher in voltage level than the system voltage An input/output (I/O) buffer is provided for use in an integrated circuit, which is designed in particular to be capable of accepting an input logic signal voltage higher in voltage level than the system voltage. The I/O buffer is designed in such a manne... | 01/04/2000 |
