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| Number | Title | Issue Date |
| 7876128 | Voltage sequence output circuit A voltage sequence output circuit includes a sequence control circuit and a number of voltage output circuits. The sequence control circuit includes a first NOR gate, and the first NOR gate includes a number of the input terminals. The voltage output circuits each i... | 01/25/2011 |
| 7667489 | Power-on reset circuit for a voltage regulator having multiple power supply voltages A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated wit... | 02/23/2010 |
| 7463063 | Semiconductor device In normal operation, an internal circuit operates in synchronism with a clock CK, so that switching operation of the output circuit is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit to a three-state c... | 12/09/2008 |
| 7403036 | Interface circuit As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control ena... | 07/22/2008 |
| 7372294 | On-die termination apparatus An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding uni... | 05/13/2008 |
| 7336109 | High voltage tolerant port driver A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the ... | 02/26/2008 |
| 7301381 | Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ... | 11/27/2007 |
| 7271703 | 2-bit binary comparator and binary comparing device using the same A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary com... | 09/18/2007 |
| 7271504 | Power-on reset semiconductor and method of controlling power supply voltage A semiconductor integrated circuit includes a first logic circuit to which a first power supply voltage is applied and which outputs a first signal, a first level conversion circuit to which the first power supply voltage and a second power supply voltage having an ... | 09/18/2007 |
| 7262750 | Current-driven OLED panel and related pixel structure A display apparatus includes a light-emitting device, a first scan line for transferring a first signal to select the light-emitting device, a data line for transferring a data current signal to drive the light-emitting device, a first transistor having a gate coupl... | 08/28/2007 |
| 7248076 | Dual-voltage three-state buffer circuit with simplified tri-state level shifter A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic con... | 07/24/2007 |
| 7239177 | High voltage tolerant off chip driver circuit An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the dr... | 07/03/2007 |
| 7233178 | Power-on solution to avoid crowbar current for multiple power supplies' inputs/outputs Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A... | 06/19/2007 |
| 7231336 | Glitch and metastability checks using signal characteristics In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circu... | 06/12/2007 |
| 7227384 | Scan friendly domino exit and domino entry sequential circuits A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an eval... | 06/05/2007 |
| 7208978 | Semiconductor device In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting... | 04/24/2007 |
| 7167038 | Power efficiency control output buffer A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the buffer operating efficiency. The technique is implemented to allow for a reduction of power associated wit... | 01/23/2007 |
| 7142132 | Methods and systems for multi-state switching using at least one ternary input and at least one discrete input Systems, methods and devices are described for placing a controlled device into a desired operating state in response to the position of a multi-position actuator. Two or more switch contacts provide input signals representative of the position of the actuator. Cont... | 11/28/2006 |
| 7138830 | Supply enabled optimization output buffer An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level an... | 11/21/2006 |
| 7098833 | Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid... | 08/29/2006 |
| 7096122 | Method for producing full field radial grid for hydrocarbon reservoir simulation A method producing full field radial grid includes both aerial and vertical gridding to divide a reservoir structure into simulation grid cells. The aerial gridding is performed by 1) specifying a reservoir boundary (including faults) and well locations; 2) distribu... | 08/22/2006 |
| 7049847 | Semiconductor device A semiconductor device including a tristate buffer circuit, which includes, on an output stage, at least a first transistor (P1) for pull-up driving and a second transistor (N1) for pull-down driving, in which, when a control signal (EN) is of a value ... | 05/23/2006 |
| 7046036 | Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications An output buffer circuit with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed. Because power supply voltage of PCI-X is at 3.3V, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuit in a 0.13 μm 1... | 05/16/2006 |
| 7034583 | Versatile system for output energy limiting circuitry The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure (102) adapted to drive an output load (104). A transconductance component (106 | 04/25/2006 |
| 7035953 | Computer system architecture with hot pluggable main memory boards The specification discloses a server system implementing hot pluggable memory boards in an architecture using X86 processors and off-the-shelf operating system, such as Windows® or Netware, which do not support hot plugging operations. Thus, the specification discl... | 04/25/2006 |
| 7030643 | Output buffer circuits including logic gates having balanced output nodes A buffer circuit may include an output terminal, a pull-up transistor, a pull-down transistor, and first and second logic gates. The pull-up transistor is connected between the output terminal and a supply voltage, and the pull-up transistor pulls the output termina... | 04/18/2006 |
| 7012449 | Input and output driver An input and output driver is disclosed which includes comprising a DQ switch capable of reducing a total input capacitance Cin by electrically isolating an output driver from a DQ pad using the DQ switch in a writing mode to reduce the capacitance due to the output... | 03/14/2006 |
| 7013402 | System and method for sequencing of signals applied to a circuit A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltag... | 03/14/2006 |
| 7005892 | Circuit technique for high speed low power data transfer bus A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, an... | 02/28/2006 |
| 7005897 | Output circuit The present invention relates to an output circuit. A first external power is supplied to be used as a second external power in a normal operating mode, an the supply of the power is shut off and an output driver is made to have a HIGH impedance state in a deep powe... | 02/28/2006 |
| 6975147 | Data output circuit with reduced output noise A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level... | 12/13/2005 |
| 6972593 | Method and apparatus for protecting a circuit during a hot socket condition The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital ... | 12/06/2005 |
| 6949946 | Integrated semiconductor circuit and method for functional testing of pad cells An integrated semiconductor circuit includes pad cells each having a connecting pad and an output driver. A transmission response of the pad cells is to be tested in a test mode. A signal transmitter is provided in order to produce periodic signal sequences. A perio... | 09/27/2005 |
| 6882177 | Tristate structures for programmable logic devices A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be c... | 04/19/2005 |
| 6870400 | Supply voltage detection circuit A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from... | 03/22/2005 |
| 6842038 | Self optimizing off chip driver The present invention provides apparatus and methods to eliminate a required “dead cycle” or “living cycle” during transfer of control from a first source terminated driver to a second source terminated driver on a bidirectional signaling conductor. On a las... | 01/11/2005 |
| 6838906 | I/O buffer with variable conductivity A driver structure for an I/O buffer circuit is disclosed. The driver structure includes a pre-push-pull driver and a post-push-pull driver. A delay circuit along is connected in series between the input signals of the pre-push-pull driver and the post-push-pull dri... | 01/04/2005 |
| 6803789 | High voltage tolerant output buffer The present invention discloses a high voltage tolerant output buffer, which is compatible with a 5-volt input signal on its output node while operating with a 3.3-volt power supply. The high voltage tolerant output buffer includes a NAND gate, a NOR gate, a pair of... | 10/12/2004 |
| 6803783 | Time borrowing using dynamic clock shift for bus speed performance An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a syste... | 10/12/2004 |
| 6686767 | Apparatus and method for controlling a three-state bus A signal control circuit includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each signal line of the set of signal lines. A programmable sync... | 02/03/2004 |
