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| Number | Title | Issue Date |
| 5025179 | ECL clamped cutoff driver circuit An ECL cutoff driver circuit for an ECL gate coupled between ECL high and low potential power rails includes a cutoff clamp circuit. The ECL gate with differential signal inputs and at least one output node is coupled for delivering ECL logic output signa... | 06/18/1991 |
| 5023487 | ECL/TTL-CMOS translator bus interface architecture Described is an architecture for translating between ECL and TTL/CMOS signal levels in which the control signal applied to the translating circuitry is of the same type as the output signal of the device in which the architecture is used.... | 06/11/1991 |
| 5021683 | Circuit arrangement comprising two parallel branches for transmitting a binary signal A circuit arrangement for transmitting in an undisturbed manner a binary signal through two parallel branches even in case of breakdown, failure or interruption of operating voltages of individual components of a branch, and also to enable a disturbance-f... | 06/04/1991 |
| 5017813 | Input/output module with latches An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer... | 05/21/1991 |
| 5013938 | ECL cutoff driver circuit with reduced stanby power dissipation The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit p... | 05/07/1991 |
| 5006731 | Three state emitter coupled logic circuit with a small amount of current consumption A three state emitter coupled logic circuit has a logic circuit responsive to an input logic signal and a three state control signal, a difference circuit formed by two series combination of resistors and bipolar transistors coupled in parallel as well as... | 04/09/1991 |
| 4998026 | Driver circuit for in-circuit overdrive/functional tester A driver circuit for use in a circuit board tester which tester can perform both functional and in-circuit tests on a given device under test (DUT). The tester provides a test signal representative of a command for the driver circuit to provide logic high... | 03/05/1991 |
| 4996452 | ECL/TTL tristate buffer An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL i... | 02/26/1991 |
| 4992679 | Programming logic device with multiple independent feedbacks per input/output terminal A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function... | 02/12/1991 |
| 4980579 | ECL gate having dummy load for substantially reducing skew An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.... | 12/25/1990 |
| 4980581 | Differential ECL bus tri-state detection receiver A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detectio... | 12/25/1990 |
| 4973862 | High speed sense amplifier A novel sense amplifier is taught which minimizes power consumption by causing selected current sources to conduct current only when an input signal of a selected state is present. The speed of the circuit is fast because capacitance on the critical nodes... | 11/27/1990 |
| 4973904 | Test circuit and method A test circuit for the output buffer of an integrated circuit permits testing for faults in the electrical connection of the output buffer to external conductors on a printed circuit board and for faults in the output buffer itself. A tester device suppli... | 11/27/1990 |
| 4967102 | BiCMOS power up 3-state circuit having no through current in the disabled mode A power-up 3-state circuit implemented with BiCMOS techniques is described. The circuit disables itself and draws no through current once the operating level of the applied supply voltage is achieved.... | 10/30/1990 |
| 4959565 | Output buffer with ground bounce control A novel output buffer is described which includes a plurality of pull up transistors connected in parallel and/or a plurality of pull down transistors connected in parallel. A desired amount of resistance is included in the path connecting the gates of th... | 09/25/1990 |
| 4952818 | Transmission line driver circuits A driver circuit is provided which includes an output stage having first and second transistors and an output terminal, the first transistor being of a first type conductivity is coupled from the output terminal to a first point of reference potential and... | 08/28/1990 |
| 4945264 | Interface control circuit with active circuit charge or discharge An interface control circuit comprising a buffer, an inverter, an OR gate and delay means. The interface control circuit can be utilized in digital systems for communication handshaking such that a buffer output current will actively flow through line str... | 07/31/1990 |
| 4941126 | Weak/strong bus driver Circuit and method is disclosed which prevents contention on a pulse-code modulated (PCM) bus, when different drivers are transmitting during adjacent time slots. The driver circuit switches automatically from a strong driver to a weak driver depending on... | 07/10/1990 |
| 4933577 | Output circuit for a programmable logic array An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset inp... | 06/12/1990 |
| 4933579 | Output circuit for a semiconductor device for reducing rise time of an output signal An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, comprises first circuit responsive to the input signal for generating a first signal including a low impedance portion corresponding t... | 06/12/1990 |
| 4931672 | True TTL to true ECL bi-directional tristatable translator driver circuit The present invention provides an integrated circuit that has both driver and receiver functions. The circuit of the present invention has two interrelated parts. The first part of the circuit converts true TTL signals to true ECL signals. The second part... | 06/05/1990 |
| 4885485 | CMOS Output buffer providing mask programmable output drive current A CMOS output buffer interconnects binary logic integrated circuits. The output buffer is readily configurable through variation of a single metallization mask during fabrication for providing interconnection of integrated circuits through either transmis... | 12/05/1989 |
| 4883990 | ECL-TTL level converter An ECL-TTL level converter having a three-state output level is disclosed. A circuit provided in the converter for forming the three-state output level includes a function for protecting IC's connected to the output terminal of the converter when an negat... | 11/28/1989 |
| 4870301 | Differential emitter-coupled-logic bus driver An Emitter-Coupled-Logic (ECL) bus driver circuit provides differential ECL output signals designed for bus driving applications in response to receiving differential logic input signals and when disabled by a disabling signal places the differential outp... | 09/26/1989 |
| 4864166 | Tri-state logic level converter circuit A logic level converter circuit has a first state (E1 low, E2 low) which produces a high level on the output TTL S, a second state (E1 high, E2 low) which produces a low level on the output S, and a third state ... | 09/05/1989 |
| 4860309 | Trinary bus communication system Trinary digital information is communicated over a pair of electrically conductive lines terminated line to line at at least one extremity by an impedance which generally matches the characteristic impedance of the two lines with respect to each other. On... | 08/22/1989 |
| 4857776 | True TTL output translator-driver with true ECL tri-state control The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. ... | 08/15/1989 |
| 4849659 | Emitter-coupled logic circuit with three-state capability An ECL circuit (301) formed with a pair of emmitter-coupled bipolar transistors (Q1A and Q1B), a main current source (26), a resistor (R1A), and an output transistor (Q2) contains a switching stage (38) for plac... | 07/18/1989 |
| 4841484 | Tri-state IIL gate A semiconductor integrated circuit device comprising a logic circuit which is constituted by using tri-state IIL gates. The tri-state IIL gates are particularly arranged to have first and second inputs. If the second input has a first level, the circuit w... | 06/20/1989 |
| 4839538 | Impact bipolar integrated circuit designed to eliminate output glitches caused by negative chip ground spikes The disclosure relates to a circuit for compensation for ground glitches in an integrated circuit wherein there is provided a glitch fix circuit wherein a node is responsive to a negative shift in the level of ground relative to Vcc to turn on a transisto... | 06/13/1989 |
| 4839540 | Tri-state output circuit A tri-state output circuit comprising an input section having complementary field effect transistors which constitute NOR gate and investor circuits, a control section having first and second current control circuits, and an output section having bipolar ... | 06/13/1989 |
| 4814638 | High speed digital driver with selectable level shifter A driver is utilized at the output of a digital word generator for translating a digital word to selectable voltage levels in accordance with a particular unit connected to the output of the driver and undergoing diagnostic testing. The driver has a separ... | 03/21/1989 |
| 4801825 | Three level state logic circuit having improved high voltage to high output impedance transition A circuit is provided which comprises a push-pull switching stage responsive to applied control signals for alternately establishing high and low output voltage levels at an output of the circuit responsive to control signals which are derived from an app... | 01/31/1989 |
| 4800294 | Pin driver circuit A pin driver circuit for driving a digital integrated circuit is capable of producing symmetrical rise and fall characteristics, yet is suitable for implementation in monolithic bipolar integrated circuits. This circuit includes a pair of matched transcon... | 01/24/1989 |
| 4797581 | Circuit for converting tri-state signals into binary signals A circuit for converting tri-state signals into binary signals comprises two current sources, each of which is connected to a common input via a respective diode path and to a respective output transistor via a further respective diode path. Depending on ... | 01/10/1989 |
| 4791314 | Oscillation-free, short-circuit protection circuit A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase th... | 12/13/1988 |
| 4772811 | Programmable logic device A programmable logic device of a single semiconductor chip includes a plurality of programmable AND-OR logic blocks, each block including an AND gate array and an OR gate array and at least a pair of input and output lines; a plurality of input/output buf... | 09/20/1988 |
| 4766334 | Level clamp for Tri-state CMOS bus structure A combination non-inverting driver and a resistor ensures the locking of a free floating bus line of a CMOS system into whatever logic state the bus line was last driven.... | 08/23/1988 |
| 4760282 | High-speed, bootstrap driver circuit A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase th... | 07/26/1988 |
| 4758746 | Programmable logic array with added array of gates and added output routing flexibility A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set o... | 07/19/1988 |
