Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8018250 | Input/output block and operation thereof An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to th... | 09/13/2011 |
| 7948269 | System and method for open drain/open collector structures in an integrated circuit In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q1) that has a first terminal coupled to a bus line terminal, and a second driving device (Q2) that has a first terminal coupled to the bus line terminal. T... | 05/24/2011 |
| 7868656 | Hot plug control apparatus and method An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic oper... | 01/11/2011 |
| 7786758 | Asynchronous clock gate with glitch protection A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input si... | 08/31/2010 |
| 7768304 | Tri-state circuit using nanotube switching elements Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tr... | 08/03/2010 |
| 7688109 | Semiconductor memory device The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which ... | 03/30/2010 |
| 7622953 | Test circuit, selector, and semiconductor integrated circuit A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical valu... | 11/24/2009 |
| 7541835 | Circuit technique to achieve power up tristate on a memory bus Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage s... | 06/02/2009 |
| 7436207 | Integrated circuit device having at least one of a plurality of bond pads with a selectable plurality of input-output functionalities An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator f... | 10/14/2008 |
| 7432731 | Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive... | 10/07/2008 |
| 7432739 | Low voltage complementary metal oxide semiconductor process tri-state buffer A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second cont... | 10/07/2008 |
| 7414434 | Input circuit An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state. The input circuit includes: four resistor elements serially provided between differ... | 08/19/2008 |
| 7403036 | Interface circuit As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control ena... | 07/22/2008 |
| 7373569 | Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also com... | 05/13/2008 |
| 7327167 | Anticipatory programmable interface pre-driver This document discusses, among other things, a circuit for selectively engaging an output section based on a received data signal. The output is driven to a high-impedance state in anticipation of a possible change in driving agent. An output section includes active... | 02/05/2008 |
| 7319344 | Pulsed flop with embedded logic In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of th... | 01/15/2008 |
| 7304501 | Method and apparatus for protecting a circuit during a hot socket condition The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital ... | 12/04/2007 |
| 7295036 | Method and system for reducing static leakage current in programmable logic devices A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality o... | 11/13/2007 |
| 7292067 | Method and apparatus for buffering bi-directional open drain signal lines A buffer system includes a logic adjusting circuit for translating a first logic level of a first component to a second logic level of a second component. The first and second logic level values are substantially different, and the buffer system has no directional c... | 11/06/2007 |
| 7293127 | Method and device for transmitting data using a PCI express port A data port operates to support symmetric PCI Express-type data transfers when in a first mode of operation. When in a second mode of operation, at least a portion of the data port connections are used to support an asymmetric PCI Express-type data transfer. The asy... | 11/06/2007 |
| 7288961 | Tri-state circuit using nanotube switching elements Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tr... | 10/30/2007 |
| 7279953 | Current switch and method of driving the same A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the s... | 10/09/2007 |
| 7276939 | Semiconductor integrated circuit A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions ... | 10/02/2007 |
| 7269040 | Static content addressable memory cell A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of ... | 09/11/2007 |
| 7265575 | Nanotube-based logic driver circuits Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each ... | 09/04/2007 |
| 7262637 | Output buffer and method having a supply voltage insensitive slew rate An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which ... | 08/28/2007 |
| 7259588 | Tri-state detection circuit for use in devices associated with an imaging system A tri-state detection circuit includes a first input port for receiving a tri-state input signal, a clock input port for receiving a clocking signal, a first output port, a second output port coupled to the first input port, a D-flip-flop and a buffer. The D-flip-fl... | 08/21/2007 |
| 7245281 | Drive circuit device for display device, and display device using the same A drive circuit device for a display device which drives a plurality of source bus lines provided on a display panel includes a driver unit that receives a clock signal, a data signal and a control signal, sequentially fetches the data signal, and generates drive si... | 07/17/2007 |
| 7239177 | High voltage tolerant off chip driver circuit An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the dr... | 07/03/2007 |
| 7215149 | Interface circuitry for electrical systems An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, where... | 05/08/2007 |
| 7212038 | Line driver for transmitting data A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a ... | 05/01/2007 |
| 7208977 | Tristate startup operating mode setting device A tristate operating mode setting device is proposed, which is designed for use with an electronic circuit unit for providing the electronic circuit unit with a tristate operating mode setting function, and which is characterized by the utilization of a specially-de... | 04/24/2007 |
| 7205793 | Self-programmable bidirectional buffer circuit and method The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes.... | 04/17/2007 |
| 7202702 | Output buffer slew rate control using clock signal A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer. ... | 04/10/2007 |
| 7196556 | Programmable logic integrated circuit devices with low voltage differential signaling capabilities A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used indivi... | 03/27/2007 |
| 7174445 | Flash memory card with enhanced operating mode detection and user-friendly interfacing system An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significan... | 02/06/2007 |
| 7167026 | Tri-state circuit using nanotube switching elements Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tr... | 01/23/2007 |
| 7164292 | Reducing electrical noise during bus turnaround in signal transfer systems Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the driver... | 01/16/2007 |
| 7161385 | Circuit elements and parallel computational networks with logically entangled terminals The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical values of the other variables in the set. A circuit element according t... | 01/09/2007 |
| 7154296 | Integrated bus hold and pull-up resistor Circuits, methods, and apparatus that combine a bus hold and a pull-up circuit in a die area efficient and conflict free manner. An exemplary embodiment of the present invention combines a bus hold resistor with a pull-up resistor. The resistor is connected between ... | 12/26/2006 |
