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| Number | Title | Issue Date |
| 8159268 | Interconnect structures for metal configurable integrated circuits Interconnect structure comprising buffers for a semiconductor device is disclosed. The buffer comprises: an input and an output; and a programmable interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plural... | 04/17/2012 |
| 8138792 | Gate drive circuit, display substrate having the same, and method thereof A gate drive circuit includes a shift register, a clock wiring and a start wiring. The shift register includes a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals. The clock wiring is extended along the first... | 03/20/2012 |
| 8106683 | One phase logic Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. ... | 01/31/2012 |
| 7977973 | Electronic basic unit for a system on chip An electronic basic unit for a system on chip comprises a semiconductor substrate and an area on the semiconductor substrate. The area is bounded by a geometric basic shape and the electronic basic unit is formed on the semiconductor substrate and has the form of an... | 07/12/2011 |
| 7977974 | Integrated circuit device and electronic instrument An integrated circuit device includes a digital power supply regulation circuit, an analog power supply regulation circuit, a control logic circuit, an analog circuit, and a power supply wiring region. A digital power supply line which supplies a digital power suppl... | 07/12/2011 |
| 7932746 | One phase logic Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. ... | 04/26/2011 |
| 7839169 | Programmable logic device with embedded switch fabric The invention in the simplest form is a programmable logic device comprising logic blocks configured substantially in a plane, external I/O endpoints, and embedded switched fabrics which provide non-contentious connection between the logic blocks and between logic b... | 11/23/2010 |
| 7750676 | Embedded system and control method therefor An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information storage storing setting information including information of a storage dev... | 07/06/2010 |
| 7733125 | Programmable logic device with embedded switch fabric The invention in the simplest form is a programmable logic device consisting of gate arrays, external I/O endpoints, and an embedded switch fabric configurable for connecting gates to gates, endpoints to endpoints and gates to endpoints. The architecture may employ ... | 06/08/2010 |
| 7616027 | Configurable circuits, IC's and systems Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection sche... | 11/10/2009 |
| 7602216 | Integrated circuit device and electronic instrument An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor, a second predriver that drives the P-type power MOS transistor, a lo... | 10/13/2009 |
| 7446563 | Three dimensional integrated circuits A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor. | 11/04/2008 |
| 7439774 | Multiplexing circuit for decreasing output delay time of output signal Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, a... | 10/21/2008 |
| 7432734 | Versatile logic element and logic array block An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic e... | 10/07/2008 |
| 7432735 | Programmable gate array apparatus and method for switching circuits A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group re... | 10/07/2008 |
| 7434192 | Techniques for optimizing design of a hard intellectual property block for data transmission Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes su... | 10/07/2008 |
| 7429870 | Resilient integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/30/2008 |
| 7425843 | Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM) Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorpor... | 09/16/2008 |
| 7423453 | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can b... | 09/09/2008 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting... | 09/02/2008 |
| 7420389 | Clock distribution in a configurable IC Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for configurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least on... | 09/02/2008 |
| 7417457 | Scalable non-blocking switching network for programmable logic A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors i... | 08/26/2008 |
| 7417454 | Low-swing interconnections for field programmable gate arrays An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shift... | 08/26/2008 |
| 7417453 | System and method for dynamically executing a function in a programmable logic array A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into mult... | 08/26/2008 |
| 7417456 | Dedicated logic cells employing sequential logic and control logic functions A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic functio... | 08/26/2008 |
| 7414431 | Dedicated logic cells employing configurable logic and dedicated logic functions A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic functio... | 08/19/2008 |
| 7414433 | Interconnect structure enabling indirect routing in programmable logic An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable s... | 08/19/2008 |
| 7414432 | Dedicated logic cells employing sequential logic and control logic functions A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic functio... | 08/19/2008 |
| 7408383 | FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect rout... | 08/05/2008 |
| 7408382 | Configurable circuits, IC's, and systems Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The... | 08/05/2008 |
| 7408381 | Circuit for and method of implementing a plurality of circuits on a programmable logic device A circuit for implementing a plurality of circuits on a programmable logic device, the circuit comprising a first circuit implemented on a first portion of the programmable logic device; a second circuit implemented on a second portion of the programmable logic devi... | 08/05/2008 |
| 7400166 | Digital logic unit reconfigurable in nonvolatile fashion A circuit analyzes the configured status of cells with a magnetic layer system, resistance of which may be altered by magnetic field pulses, forming a first line branch with data cells arranged in series and a second line branch with configurable cells arranged in s... | 07/15/2008 |
| 7397276 | Logic block control architectures for programmable logic devices Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodime... | 07/08/2008 |
| 7394288 | Transferring data in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction ... | 07/01/2008 |
| 7391236 | Distributed memory in field-programmable gate array integrated circuit devices Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data pa... | 06/24/2008 |
| 7388401 | Input/output circuit device An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and d... | 06/17/2008 |
| 7385419 | Dedicated input/output first in/first out module for a field programmable gate array A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-i... | 06/10/2008 |
| 7385417 | Dual slice architectures for programmable logic devices Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of t... | 06/10/2008 |
| 7382157 | Interconnect driver circuits for dynamic logic Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driv... | 06/03/2008 |
| 7378872 | Programmable logic device architecture with multiple slice types Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodime... | 05/27/2008 |
