Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 8159267 | Semiconductor device, display device, and electronic device To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display devic... | 04/17/2012 |
| 8143915 | IC with deskewing circuits Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. M... | 03/27/2012 |
| 8058901 | Latch structure, frequency divider, and methods for operating same A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic le... | 11/15/2011 |
| 8058902 | Circuit for aligning input signals A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the CGC, are responsive to first type of edge of the clock si... | 11/15/2011 |
| 8035415 | Shift register and semiconductor display device The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The... | 10/11/2011 |
| 7999571 | State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the ... | 08/16/2011 |
| 7977972 | Ultra-low power multi-threshold asynchronous circuit design A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extrem... | 07/12/2011 |
| 7961005 | Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activat... | 06/14/2011 |
| 7919981 | Integrated circuit design based on scan design technology An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal con... | 04/05/2011 |
| 7893713 | Mixed signal integrated circuit This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analog and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circu... | 02/22/2011 |
| 7876127 | Automatic hold time fixing circuit unit An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connec... | 01/25/2011 |
| 7843217 | Shift register and semiconductor display device The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The... | 11/30/2010 |
| 7843218 | Data latch with structural hold A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latc... | 11/30/2010 |
| 7839168 | Circuit with parallel functional circuits with multi-phase control inputs A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circu... | 11/23/2010 |
| 7834660 | State machines using resistivity-sensitive memories State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the ... | 11/16/2010 |
| 7825689 | Functional-input sequential circuit An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a c... | 11/02/2010 |
| 7812636 | Method and device for generating pseudo-random binary data A device for generating k-bit parallel pseudo-random data includes “n” registers, from the first through the n-th registers (“n” is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an... | 10/12/2010 |
| 7808272 | Integrated circuit An integrated circuit for analyzing the waveform of an input signal includes a first storage circuit and a second storage circuit that are each supplied with the input signal. The first and second storage circuits are controlled by a clock signal. The first storage ... | 10/05/2010 |
| 7808273 | Reducing leakage power in low power mode Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock sig... | 10/05/2010 |
| 7800406 | Apparatus, circuit and method of transmitting signal An apparatus includes a transmission circuit which transmits a data by a differential signal, and a control circuit which halts a portion of the differential signal under a predetermined condition. ... | 09/21/2010 |
| 7795913 | Programmable latch based multiplier A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output c... | 09/14/2010 |
| 7777520 | System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latc... | 08/17/2010 |
| 7772882 | Robust and economic solution for FPGA bit file upgrade A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup versi... | 08/10/2010 |
| 7768303 | Apparatus, circuit and method of monitoring performance An apparatus includes a first sequential circuit which captures an input signal according to a first clock signal, a second sequential circuit which captures the input signal according to a second clock signal and outputs the captured input signal to a logic circuit... | 08/03/2010 |
| 7764084 | Apparatus for reducing power consumption with configurable latches and registers Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. Th... | 07/27/2010 |
| 7750675 | Method for running state machines A method and computer program product for running state machines by the steps of running at least a first and a second state machine in parallel, observing at least the first state machine for at least one first synchronization rule, and changing the state of the se... | 07/06/2010 |
| 7728627 | Intelligent embedded power rail and control signal sequencer A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable s... | 06/01/2010 |
| 7692449 | Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style... | 04/06/2010 |
| 7688107 | Shift register, display device, and electronic device The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n−1)-th stage operates in accordance with the first output from the previous stage, an output from the second c... | 03/30/2010 |
| 7683666 | Circuit component with programmable characteristics and method of operating same A method and apparatus involve operating a circuit that includes a first portion and a second portion, including: operating the first portion in synchronism with a clock signal; maintaining in the first portion a logical value that can vary dynamically; and operatin... | 03/23/2010 |
| 7671627 | Superscale processor performance enhancement through reliable dynamic clock frequency tuning In the case of a pipelined processor, a performance gain is achievable through dynamically generating a main clock signal associated with a synchronous logic circuit and generating at least one backup register clock signal, the backup register clock signal at the sa... | 03/02/2010 |
| 7656194 | Shift register circuit A shift register circuit comprising a plurality of stages dependently connected to an initial input signal or an output signal of a previous stage and connected to first and second clock signals which are mutually inverted. Each stage includes eight switching device... | 02/02/2010 |
| 7656195 | Latch circuit, flip-flop circuit including the same, and logic circuit Disclosed herein is a latch circuit including a switching circuit for switching output/non-output of an externally inputted external signal based on a predetermined control signal, a state retaining circuit for inputting a signal outputted from the switching circuit... | 02/02/2010 |
| 7626420 | Method, apparatus, and system for synchronously resetting logic circuits An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal ... | 12/01/2009 |
| 7605607 | State machine and system and method of implementing a state machine A system and method for implementing a state machine including a plurality of states, the state machine configured to transition from a present state to a next state in response to input. One embodiment of the system includes a plurality of state elements, each of t... | 10/20/2009 |
| 7602215 | Shift register and semiconductor display device The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The... | 10/13/2009 |
| 7592836 | Multi-write memory circuit with multiple data inputs Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a first data input and to a second data input. The first data input is introduced into the feedback loop at a first set of points, and the second da... | 09/22/2009 |
| 7479803 | Techniques for debugging hard intellectual property blocks Techniques are provided to hardware debug a programmable logic integrated circuit that includes a hardware intellectual property block (HIP). The HIP includes a logic circuit and state machine(s). The state machine outputs state machine information depending on sele... | 01/20/2009 |
| 7474123 | Method for reducing power consumption with configurable latches and registers Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. Th... | 01/06/2009 |
| 7459936 | Fast/slow state machine latch A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a del... | 12/02/2008 |
