Bizarre Patents
A simulation environment for the sport of boxing utilizing a robotic machine interface system which carries a person
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5379399 | FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparato... | 01/03/1995 |
| 5377206 | Multiple-channel fault-tolerant clock system A fault-tolerant clock having at least four channels, each providing its own clock output, and yet all clock output signals of all functioning channels being coherent with one another. One clock functions as a master with the other clocks of the remaining... | 12/27/1994 |
| 5371413 | Process and arrangement for the Boolean realization of adaline-type neural networks A process is stated with which ADALINE-type neural networks whose inputs are Boolean variables can be realized using Boolean functions. In addition, a purely digital circuit arrangement for realizing ADALINE-type neural networks is stated. The digital cir... | 12/06/1994 |
| 5355438 | Weighting and thresholding circuit for a neural network An analog circuit which performs weighting and thresholding for a neural network. Each neuron of the neural network includes an operational amplifier receiving an input signal, the output of which is connected to a transistor. The transistor conducts only... | 10/11/1994 |
| 5353383 | Neural network circuit A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof b... | 10/04/1994 |
| 5347180 | Three-input signal section, application to a selector with N inputs and to a poller with N inputs A three-input signal selector formulates two output signals from three input signals. The selector is useful in pollers of various types.... | 09/13/1994 |
| 5319587 | Computing element for neural networks A computing element for use in an array in a neural network. Each computing element has K (K>1) input signal terminals, K input backpropagated signal terminals, K output backpropagated signal terminals and at least one output terminal. The input terminals... | 06/07/1994 |
| 5315163 | Analogic neuronal network The network comprises cells each constituted by a first channel (4, 4') of a material having selectively a superconductive state and a resistive state, refrigeration apparatus to maintain the first channel at a temperature below that which ensures superco... | 05/24/1994 |
| 5315162 | Electrochemical synapses for artificial neural networks An electrochemical synapse adapted for use in a neural network which includes an input terminal and an output terminal located at a distance of less than 100 microns from the input terminal. A permanent interconnect having controllable conductivity is loc... | 05/24/1994 |
| 5312684 | Threshold switching device This invention relates to a method of forming a threshold switching device which exhibits negative differential resistance and to the devices formed thereby. The method comprises depositing a silicon dioxide film derived from hydrogen silsesquioxane resin... | 05/17/1994 |
| 5305235 | Monitoring diagnosis device for electrical appliance A monitoring diagnostic device for an electrical appliance such as gas insulated switchgear includes a sensor, such as an acceleration sensor, and a neural network including an input layer, an intermediate layer, and an output layer, each consisting of a ... | 04/19/1994 |
| 5274744 | Neural network for performing a relaxation process In accordance with the present invention, a neural network comprising an array of neurons (i.e. processing nodes) interconnected by synapses (i.e. weighted transmission links) is utilized to carry out a probabilistic relaxation process. The inventive neur... | 12/28/1993 |
| 5265044 | High speed arithmetic and logic generator with reduced complexity using negative resistance A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremel... | 11/23/1993 |
| 5258657 | Neuron circuit A semiconductor device of this invention comprises on a substrate a first semiconductor region of one conductive type, first source and drain regions of the opposite conductive type formed in said semiconductor region, a first gate electrode formed in a r... | 11/02/1993 |
| 5258946 | Content-addressable memory A measure of the correlation or degree of closeness between an input data pattern and a stored data pattern is achieved directly from content-addressable memory cells which are realized in accordance with the principles of the present invention to provide... | 11/02/1993 |
| 5255349 | Electronic neural network for solving "traveling salesman" and similar global optimization problems This invention is a novel high-speed neural network based processor for solving the "traveling salesman" and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the f... | 10/19/1993 |
| 5248956 | Electronically controllable resistor An electronically controllable resistor (ECR) which functions as a fixed or variable resistor over a wide range of operating conditions. The value of the resistance may be altered in a highly linear fashion by altering a digital input thereto. The ECR uti... | 09/28/1993 |
| 5235220 | Majority decision method and circuit wherein least possible flip-flops are used On determining an entire majority of five i-th received data bits which correspond to an i-th original data bit repeatedly received five times, first through I-th received data bits of a first received frame are stored in a main buffer (41) as first throu... | 08/10/1993 |
| 5235672 | Hardware for electronic neural network This application discloses hardware suitable for use in a neural network system. It makes use of Z-technology modules, each containing densely packaged electronic circuitry. The modules provide access planes which are electrically connected to circuitry l... | 08/10/1993 |
| 5218245 | Programmable neural logic device A programmable logic cell, compatible with LSSD (Level Sensitive Scan Design) technique, is described whose internal logic function can be initially loaded from an EPROM or external processor. The output or contents of one cell can be connected to another... | 06/08/1993 |
| 5218440 | Switched resistive neural network for sensor fusion An electronic image processing system uses data provided by one or more sensors to perform cooperative computations and improve image recognition performance. A smoothing resistive network, which may comprise an integrated circuit chip, has switching elem... | 06/08/1993 |
| 5195170 | Neural-network dedicated processor for solving assignment problems A neural network processor for solving first-order competitive assignment problems consists of a matrix of N×M processing units, each of which corresponds to the pairing of a first number of elements of {Ri } with a second number of elements {... | 03/16/1993 |
| 5166539 | Neural network circuit A neural network circuit, in which a number n of weight coefficients (Wl-wn) corresponding to a number n of inputs are provided, subtraction circuits determine the difference between inputs and the weight coefficients in each input terminal, the result th... | 11/24/1992 |
| 5164618 | Superconducting gate array cells Superconducting timed gate array cells for use in single-rail logic circuits are provided by adding inputs to modified variable threshold logic (MVTL) timed inverter circuits. Data signals which are inphase with a first phase of a power source are coupled... | 11/17/1992 |
| 5155388 | Logic gates with controllable time delay Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third l... | 10/13/1992 |
| 5153461 | Logic circuit using element having negative differential conductance A logic circuit includes n input terminals where n is an odd integer, an output terminal, and n input resistance elements respectively connected to the n input terminals. The logic circuit also includes a negative differential conductance element having a... | 10/06/1992 |
| 5126598 | Josephson integrated circuit having an output interface capable of providing output data with reduced clock rate A Josephson integrated circuit includes a Josephson logic processor operated at a first clock rate, and a latch circuit formed of Josephson devices operated at the first clock rate for receiving output data from the Josephson processor together with a sta... | 06/30/1992 |
| 5126600 | Truth value generating basic circuit suitable for analog inputs A truth value generating basic circuit according to the invention is characterized by having one or a plurality of basic function generator circuits (23, 24) which receive an analog applied input and include an operational amplifier (A1), and a... | 06/30/1992 |
| 5111082 | Superconducting threshold logic circuit A superconducting threshold logic circuit comprises current switching circuits each having a Josephson device. Bias currents of the switching circuits are varied independently to change weights for input signals. A sum of the weighted input signals are in... | 05/05/1992 |
| 5072130 | Associative network and signal handling element therefor for processing data A signal processing network circuit which may be used, for example, as a filter or an associative memory has elements (101, 102, 103, 104) each having a respective input conductor (85, 86, 87, 88) and a respective output conductor (81, 82, 83, 84) a teach... | 12/10/1991 |
| 5065040 | Reverse flow neuron A neural network is provided for performing bi-directional signal transformations through a matrix of synapses by alternately sending and receiving signal vectors therethrough via switchable driver circuits. In the forward direction, the input signal is t... | 11/12/1991 |
| 5059835 | CMOS circuit with programmable input threshold A CMOS circuit having an input threshold, the CMOS circuit including a first field-effect transistor having a source connected to a first power supply terminal, a drain connected to an output terminal, a gate connected to an input terminal, and a first ch... | 10/22/1991 |
| 5053645 | Threshold logic circuit In a threshold logic circuit, digital input signals are weighted and summed up and then the sum of weighted digital signals is compared with a threshold value. The threshold logic circuit comprises a plurality of current switching circuits and means for s... | 10/01/1991 |
| 5039870 | Weighted summation circuits having different-weight ranks of capacitive structures The input signals to the weighted summation circuitry are weighted by respective weighting factors on a digit-sliced basis. Each of the weighting factors is expressed as a respective plurality of portions of different weighting significance, the portions ... | 08/13/1991 |
| 5039871 | Capacitive structures for weighted summation as used in neural nets The capacitances of a pair of capacitors associated with a neural net is carried out in a complementary way, so the sum of the capacitances remains equal to a constant, Ck. Each of a set of component capacitors with capacitances related in acco... | 08/13/1991 |
| 4969164 | Programmable threshold detection logic for a digital storage buffer A threshold detection logic circuit of simple and economical design is disclosed that indicates when the difference in the number of first operations to be counted and the number of second operations to be counted is either greater than or equal to a thre... | 11/06/1990 |
| 4945257 | Electrically settable resistance device A device provides an electrically settable resistance and comprises first and second electrodes. Each electrode comprises a redox active material. The device further comprises means defining an environment for each electrode such that the average redox st... | 07/31/1990 |
| 4926064 | Sleep refreshed memory for neural network A method and apparatus are disclosed for implementing a neural network having a sleep mode during which capacitively stored synaptic connectivity weights are refreshed. Each neuron outputs an analog activity level, represented in a preferred embodiment by... | 05/15/1990 |
| 4896053 | Solitary wave circuit for neural network emulation A circuit for emulating a nerve cell is used to generate one or more simple neural networks. In the preferred embodiment, the circuit comprises an LC ladder circuit including one or more modules, each of the modules comprising an "L" two-port circuit comp... | 01/23/1990 |
| 4860243 | Fuzzy logic semifinished integrated circuit A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mi... | 08/22/1989 |
