"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 8421499 | Power switch ramp rate control using programmable connection to switches In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the sel... | 04/16/2013 |
| 8330487 | Semiconductor device The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first a... | 12/11/2012 |
| 8314634 | Power control block with output glitch protection Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal ope... | 11/20/2012 |
| 8081011 | Method and apparatus for regulating a power supply of an integrated circuit Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate... | 12/20/2011 |
| 8067958 | Mitigating side effects of impedance transformation circuits Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide... | 11/29/2011 |
| 8026738 | Integrated circuit with signal bus formed by cell abutment of logic cells An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal... | 09/27/2011 |
| 7986162 | Interface circuit An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level ... | 07/26/2011 |
| 7987441 | Method and architecture for power gate switch placement A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage reference... | 07/26/2011 |
| 7977969 | Circuit arrangement and method for evaluating a data signal A circuit arrangement (10) comprises a circuit terminal (11) for supplying a data signal (DATA) having digital information, a logic circuit (12) that is coupled at an input (22) to the circuit terminal (11) for supplying the digita... | 07/12/2011 |
| 7948263 | Power gating circuit and integrated circuit including same A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail ... | 05/24/2011 |
| 7928758 | Transistor gate driving circuit with power saving of power converter A transistor gate driving circuit is developed for power saving. It includes a first high-side transistor, a second high-side transistor and a low-side transistor. A voltage clamp device is connected to the gate terminal of the first high-side transistor to limit th... | 04/19/2011 |
| 7915915 | Circuit system for data transmission A differential stage circuit is disclosed, which includes a differential circuit, a current source coupled to supply, when activated, an operating current to the differential circuit, and a control circuit coupled to control activation and deactivation of the curren... | 03/29/2011 |
| 7902861 | Adiabatic CMOS design An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one... | 03/08/2011 |
| 7859300 | Input and output circuit apparatus An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal r... | 12/28/2010 |
| 7852113 | Leakage control In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply... | 12/14/2010 |
| 7834656 | Two-wire transmitter A two-wire transmitter is connected to two transmission lines which transmit an electric signal regarding a physical quantity detected by a sensor. The two-wire transmitter includes a current control section which controls a transmission current of the electric sign... | 11/16/2010 |
| 7830169 | Semiconductor device There is provided a current amount adjusting section adjusting a current amount flowing through a power supply line supplying power to an internal circuit which includes a circuit operating based on a clock signal and a ratio of consumed charge amounts by the curren... | 11/09/2010 |
| 7795906 | Leakage power management with NDR isolation devices A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device rai... | 09/14/2010 |
| 7791368 | Method and apparatus for regulating a power supply of an integrated circuit Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.... | 09/07/2010 |
| 7791369 | Semiconductor integrated circuit and operation method of the same A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block incl... | 09/07/2010 |
| 7786756 | Method and system for latchup suppression Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage... | 08/31/2010 |
| 7777518 | Semiconductor integrated circuit device A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is suppl... | 08/17/2010 |
| 7768298 | Reference voltage generators for reducing and/or eliminating termination mismatch A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connec... | 08/03/2010 |
| 7750668 | Semiconductor integrated circuit device having power reduction mechanism A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a curren... | 07/06/2010 |
| 7737720 | Virtual power rail modulation within an integrated circuit An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at ... | 06/15/2010 |
| 7728621 | Block-by-block leakage control and interface In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherei... | 06/01/2010 |
| 7719310 | Semiconductor integrated circuit device and method for manufacturing the same A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a hi... | 05/18/2010 |
| 7701245 | Enhanced voltage regulation with power supply disable capability for low-power operation A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivate... | 04/20/2010 |
| 7683659 | Integrated circuits with jitter-reducing balancing logic Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provide... | 03/23/2010 |
| 7671623 | Device for managing the consumption peak of a domain on each powering-up A device is provided for managing the current consumption peak on each powering-up of a domain in an electronic circuit. A plurality of domains are present and a global power supply grid provides power. Each domain is selectively supplied by a local supply grid conn... | 03/02/2010 |
| 7667484 | Semiconductor device reducing power consumption in standby mode A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a f... | 02/23/2010 |
| 7639039 | Semiconductor integrated circuit having current leakage reduction scheme A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The ... | 12/29/2009 |
| 7619440 | Circuit having logic state retention during power-down and method therefor A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled... | 11/17/2009 |
| 7602210 | Two-wire transmitter A two-wire transmitter for receiving power supply from an external circuit through two transmission lines and also transmitting a current signal based on the measurement value of a sensor includes a current control section to which a voltage is supplied from an exte... | 10/13/2009 |
| 7602211 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal... | 10/13/2009 |
| 7595658 | Voltage divider circuit The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least on... | 09/29/2009 |
| 7564259 | Digital circuit with dynamic power and performance control via per-block selectable operating voltage A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power suppl... | 07/21/2009 |
| 7548088 | Systems and methods for current management for digital logic devices Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information abo... | 06/16/2009 |
| 7545165 | System architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are... | 06/09/2009 |
| 7514956 | Semiconductor device A first and a second charging circuit each having a diode and a capacitor are connected to a buffer. In the first charging circuit, an overshoot based on a reflected signal generated by an output signal is stored as an electric charge to the capacitor, and in the se... | 04/07/2009 |