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| Number | Title | Issue Date |
| 7403041 | Techniques for enabling a 10BT active output impedance line driver using a low power supply A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. ... | 07/22/2008 |
| 7403040 | Reference voltage generators for reducing and/or eliminating termination mismatch A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connec... | 07/22/2008 |
| 7403033 | MOS linear region impedance curvature correction A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region... | 07/22/2008 |
| 7403034 | PVT controller for programmable on die termination Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die t... | 07/22/2008 |
| 7400165 | Method for calibrating a driver and on-die termination of a synchronous memory device An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibrat... | 07/15/2008 |
| 7400164 | Integrated circuit and method of improving signal integrity An Integrated Circuits (ICs) comprising a first output stage circuit and a second output stage circuit that share common input terminals and an output terminal of the first and second output stage circuits being selectably coupled between the input terminals and the... | 07/15/2008 |
| 7397270 | Dynamically-adjustable differential output drivers Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuit... | 07/08/2008 |
| 7394282 | Dynamic transmission line termination A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the te... | 07/01/2008 |
| 7394307 | Voltage regulator having reverse voltage protection and reverse current prevention A voltage regulator having a MOS transistor driver includes a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage in... | 07/01/2008 |
| 7391231 | Switch selectable terminator for differential and pseudo-differential signaling An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three different... | 06/24/2008 |
| 7391238 | Semiconductor memory device having pre-emphasis signal generator A semiconductor memory device includes a primary output driver which outputs a data signal through an output terminal; a secondary output driver which is connected to the output terminal and performs a pre-emphasis operation; and a pre-emphasis signal generator whic... | 06/24/2008 |
| 7391230 | Adjustment of termination resistance in an on-die termination circuit The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be p... | 06/24/2008 |
| 7391221 | On-die impedance calibration One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibr... | 06/24/2008 |
| 7391229 | Techniques for serially transmitting on-chip termination control signals Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calib... | 06/24/2008 |
| 7385414 | Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohi... | 06/10/2008 |
| 7385415 | Semiconductor integrated circuit A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting c... | 06/10/2008 |
| 7383373 | Deriving corresponding signals Apparatus used in deriving corresponding signals includes first and second circuitry. The first circuitry derives, from a source-terminated first signal driven from a Peripheral Control Interface (PCI) Express compatible source, an AC-coupled second signal. The seco... | 06/03/2008 |
| 7382152 | I/O interface circuit of integrated circuit A plurality of transistor pairs of Pch and Nch transistors are connected in series between VDD and GND. An I/O terminal is connected to each connection point of the transistor pairs. Two transistor pairs constitute one transistor set, in which each of two Pch transi... | 06/03/2008 |
| 7382153 | On-chip resistor calibration for line termination A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. Th... | 06/03/2008 |
| 7378866 | Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined ... | 05/27/2008 |
| 7375545 | Semiconductor device with bus terminating function The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance w... | 05/20/2008 |
| 7375546 | Methods of providing performance compensation for supply voltage variations in integrated circuits Methods of compensating for power supply variations in an integrated circuit. During operation of the IC die, a power supply voltage level is monitored. When the power supply voltage level drops below a specified level, a performance compensation circuit in the IC i... | 05/20/2008 |
| 7372293 | Polarity driven dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pi... | 05/13/2008 |
| 7373114 | Signal transmission circuit, signal output circuit and termination method of signal transmission circuit This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a ... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372681 | Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fi... | 05/13/2008 |
| 7372294 | On-die termination apparatus An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding uni... | 05/13/2008 |
| 7372303 | Semiconductor integrated circuit A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and ... | 05/13/2008 |
| 7372295 | Techniques for calibrating on-chip termination impedances A calibration circuit block includes a first resistor network, a second resistor network, and a feedback loop. The first resistor network includes a set of transistors and receives a constant current from a constant current source. The second resistor network receiv... | 05/13/2008 |
| 7372288 | Test apparatus for testing multiple electronic devices There is disclosed a test apparatus including a driver that outputs a test signal, a first switch that is provided between the driver and a terminal of the first device under test, a second switch that is provided between the driver and a terminal of the second devi... | 05/13/2008 |
| 7371687 | Electronic circuit device An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a... | 05/13/2008 |
| 7372292 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 05/13/2008 |
| 7369443 | Semiconductor device with adjustable signal drive power A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no ope... | 05/06/2008 |
| 7368938 | Input termination circuitry with high impedance at power off An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and ... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7368951 | Data transmission circuit and data transmission method with two transmission modes In a data transmission circuit according to the present invention, selection circuits alternately switch between transistors of a main buffer and transistors of a dummy buffer. In high-speed data transmission, a H/L transmission switch circuit outputs high-speed dat... | 05/06/2008 |
| 7368936 | Impedance match circuit An impedance match circuit having high precision without being affected by variations in manufacturing processes. The impedance match circuit includes an impedance detect circuit, a current comparator, successive approximation controller, and an impedance combinatio... | 05/06/2008 |
| 7369455 | Calibration circuit of a semiconductor memory device and method of operating the same A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compare... | 05/06/2008 |
| 7368937 | Input termination circuits and methods for terminating inputs An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage throug... | 05/06/2008 |
| 7368902 | Impedance calibration for source series terminated serial link transmitter Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors eac... | 05/06/2008 |
