Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7777517 | Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of... | 08/17/2010 |
| 7772878 | Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up o... | 08/10/2010 |
| 7772877 | Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circui... | 08/10/2010 |
| 7772876 | Configurable on-die termination Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixe... | 08/10/2010 |
| 7768297 | Multi-drop bus system A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point ... | 08/03/2010 |
| 7764083 | Digital method and device for transmission with reduced crosstalk The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or i... | 07/27/2010 |
| 7764082 | On-die termination circuit Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to inter... | 07/27/2010 |
| 7755383 | Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit conf... | 07/13/2010 |
| 7755384 | High speed IO buffer A bi-directional buffer is provided. The buffer includes a driver, a receiver, and a circuitry configured to select a driving mode in response to detecting a first condition and to select a receiving mode in response to detecting a second condition. The driving mode... | 07/13/2010 |
| 7755385 | Method for operating an electronic device with reduced pin capacitance A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output ... | 07/13/2010 |
| 7750666 | Reduced power differential type termination circuit A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second tra... | 07/06/2010 |
| 7746098 | Termination switching based on data rate Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termin... | 06/29/2010 |
| 7746096 | Impedance buffer and method An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array a... | 06/29/2010 |
| 7746097 | Transceiver having an adjustable terminating network for a control device In a transceiver for a control unit having a transceiver core for adapting the level of messages received or to be sent, an adjustable terminating network is situated in the transceiver that makes it possible to adjust at least two connection resistance values, the ... | 06/29/2010 |
| 7741866 | Load-aware circuit arrangement The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the d... | 06/22/2010 |
| 7741867 | Differential on-line termination Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit c... | 06/22/2010 |
| 7741868 | Calibration methods and circuits to calibrate drive current and termination impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates a... | 06/22/2010 |
| 7737719 | Apparatus for adjusting resistance value of a driver in a semiconductor integrated circuit An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode sig... | 06/15/2010 |
| 7733120 | Impedance adjustment circuit Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control ... | 06/08/2010 |
| 7733119 | Single-resistor static programming circuits and methods Programming circuitry 200 includes a terminal 202 for coupling to a resistor having a resistance representing a corresponding programming state. Current control circuitry 204/205 selectively passes at least one exponentially weighted current thr... | 06/08/2010 |
| 7728618 | Self-calibrating writer In accordance with the invention, a method, system and apparatus are presented that matches the output impedance of a driver to the impedance of a transmission line. A method for matching the impedance between a driver and a transmission line, wherein the transmissi... | 06/01/2010 |
| 7728619 | Circuit and method for cascading programmable impedance matching in a multi-chip system An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-... | 06/01/2010 |
| 7728620 | System including preemphasis driver circuit and method A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked ... | 06/01/2010 |
| 7724026 | Single-ended input-output block with reduced leakage current An integrated circuit has a differential I/O buffer (102) capable of being operated in a single-ended mode. The I/O buffer includes circuitry (114 or 112) for reducing leakage current between the differential I/O pins (P, N) when an undershoot e... | 05/25/2010 |
| 7719309 | Techniques for providing calibrated on-chip termination impedance Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. Th... | 05/18/2010 |
| 7719307 | Data output driving circuit of semiconductor apparatus A data output driving circuit for a semiconductor apparatus can include a code multiplier configured to multiply a received first code by a multiplication factor determined in response to a control signal and generating a second code; a signal line configured to tra... | 05/18/2010 |
| 7719308 | Semiconductor apparatus, on-die termination circuit, and control method of the same An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal; and a plurality of on-die termination blocks configured to commonly re... | 05/18/2010 |
| 7714607 | Resistor circuit, interface circuit including resistor circuit, and electronic instrument A resistor circuit includes n-stage unit circuits, each of which includes a first resistor element provided between first and second terminals, a first disconnection element provided between the second and third terminals, and a second disconnection element and a se... | 05/11/2010 |
| 7714606 | Semiconductor integrated circuit A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relativel... | 05/11/2010 |
| 7710143 | Impedance matching circuit and semiconductor memory device with the same An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a... | 05/04/2010 |
| 7710145 | Semiconductor device and method for controlling thereof A semiconductor device includes a circuit section having an output impedance which changes in accordance with a switching signal for switching between drive capabilities, and transforming an input signal into an output signal in accordance with the output impedance,... | 05/04/2010 |
| 7710144 | Controlling for variable impedance and voltage in a memory system A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an exte... | 05/04/2010 |
| 7696775 | Apparatus of impedance matching for output driver and method thereof An apparatus for impedance matching circuit is disclosed. The impedance matching apparatus has an output driver for outputting an output signal and includes an output data generator, for generating an output data signal; an output stage, for generating the output si... | 04/13/2010 |
| 7696777 | System for transmission line termination by signal cancellation A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a ... | 04/13/2010 |
| 7696776 | Circuit for generating on-die termination control signal A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal g... | 04/13/2010 |
| 7692446 | On-die termination device An on-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response t... | 04/06/2010 |
| 7692447 | Driver circuit A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to... | 04/06/2010 |
| 7688105 | Impedance matching logic An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within ... | 03/30/2010 |
| 7688104 | On-die termination device to compensate for a change in an external voltage An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared valu... | 03/30/2010 |
| 7683657 | Calibration circuit of on-die termination device A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having ... | 03/23/2010 |
