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| Number | Title | Issue Date |
| 7342411 | Dynamic on-die termination launch latency reduction Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination... | 03/11/2008 |
| 7342458 | Negative gain transductance amplifier circuit The invention proposes a negative gain transconductance amplifier circuit (1) for capacitive load that includes: an RC serial circuit connected between an input terminal (E) of the amplifier circuit and a intermediate terminal (A); an amplificat... | 03/11/2008 |
| 7343256 | Configurable voltage regulator A configurable semiconductor has a device characteristic that is controllable as a function of at least one external impedance. A measurement circuit measures an electrical characteristic of the at least one external impedance and determines a select value correspon... | 03/11/2008 |
| 7342815 | DQS signaling in DDR-III memory systems without preamble A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on an... | 03/11/2008 |
| 7339396 | Method and apparatus for ameliorating the effects of noise generated by a bus interface A method and apparatus for ameliorating the effects of noise generated by a bus interface provides improved performance of integrated circuits having other circuits sensitive to the transient noise introduced by bus signal switching. Additional signals are generated... | 03/04/2008 |
| 7339398 | Driver impedance control apparatus and system A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down arr... | 03/04/2008 |
| 7339399 | Anti-noise input/output impedance control of semiconductor circuit with reduced circuit size An impedance control system is composed of a target circuit having a controllable impedance; a replica circuit having a structure identical to the target circuit; a first binary counter providing the replica circuit with a first impedance control code indicative of ... | 03/04/2008 |
| 7339840 | Memory system and method of accessing memory chips of a memory system A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting line... | 03/04/2008 |
| 7339397 | Data output apparatus and method A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and ampl... | 03/04/2008 |
| 7336749 | Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique ... | 02/26/2008 |
| 7337216 | Electronic system architecture An electronic system architecture comprises a plurality of client devices connected in a hierarchical structure in which the client devices form nodes in the structure interconnected by communications links. One client device at the top of the hierarchical structure... | 02/26/2008 |
| 7336109 | High voltage tolerant port driver A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the ... | 02/26/2008 |
| 7335968 | High permeability composite films to reduce noise in high speed interconnects A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed ... | 02/26/2008 |
| 7336096 | System for transmission line termination by signal cancellation A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a ... | 02/26/2008 |
| 7336098 | High speed memory modules utilizing on-pin capacitors Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signa... | 02/26/2008 |
| 7332904 | On-chip resistor calibration apparatus and method An on-chip resistor is calibrated with a sense circuit that compares a resistance associated with an off-chip resistor to the on-chip resistor via a current-mirror circuit and a comparator. A digital counter circuit evaluates the comparison and adjusts its count suc... | 02/19/2008 |
| 7334137 | Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the mem... | 02/19/2008 |
| 7332932 | Serial link receiver with wide input voltage range and tolerance to high power voltage supply A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamp... | 02/19/2008 |
| 7332933 | Circuit for compensating for the declination of balanced impedance elements and a frequency mixer Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second i... | 02/19/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7330993 | Slew rate control mechanism According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate base... | 02/12/2008 |
| 7330047 | Receiver circuit arrangement having an inverter circuit A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control tran... | 02/12/2008 |
| 7330709 | Receiver circuit using nanotube-based switches and logic Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. ... | 02/12/2008 |
| 7330382 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 02/12/2008 |
| 7327016 | High permeability composite films to reduce noise in high speed interconnects An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating ma... | 02/05/2008 |
| 7327170 | Current driver A current driver outputs an output current according to a reference current. The current driver includes: a current-voltage converter; a bias-voltage generating transistor; a differential amplifier; and a driving transistor. The converter has a given resistance valu... | 02/05/2008 |
| 7324031 | Dynamic bias circuit A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The pluralit... | 01/29/2008 |
| 7323907 | Pre-emphasis driver control Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed. ... | 01/29/2008 |
| 7323900 | Semiconductor memory device for adjusting impedance of data output driver A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value u... | 01/29/2008 |
| 7323901 | Semiconductor integrated circuit device A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance wi... | 01/29/2008 |
| 7321613 | Automatic impedance matching compensation for a serial point to point link An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the ... | 01/22/2008 |
| 7321245 | Pipelined AD converter capable of switching current driving capabilities A first bias voltage generating circuit which applies a bias voltage to an amplifier circuit of an AD converter has a driving unit and a control unit. The driving unit includes a first bias circuit and a second bias circuit as a plurality of bias circuits which are ... | 01/22/2008 |
| 7319621 | Reducing DQ pin capacitance in a memory device A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, ... | 01/15/2008 |
| 7319575 | Semiconductor device This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal t... | 01/15/2008 |
| 7317351 | Low noise amplifier A low noise amplifier (LNA) is discussed. In implementations, a LNA may include a feedback section coupled to a transistor. The feedback section may have a resistive portion including a buffer and a resistor. A capacitor may be connected in parallel with the resisto... | 01/08/2008 |
| 7317934 | Configurable communications modules and methods of making the same Configurable communications modules and methods of making the same are described. In one aspect, a communications module includes a data channel and a termination impedance controller. The data channel is operable to translate data signals in at least one direction ... | 01/08/2008 |
| 7317338 | Data input buffer in semiconductor device The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing d... | 01/08/2008 |
| 7317336 | Impedance matching circuit, input-output circuit and semiconductor test apparatus A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor... | 01/08/2008 |
| 7317328 | Test device for on die termination An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination termi... | 01/08/2008 |
| 7317337 | Output driver in semiconductor device There is provided an output driver of a semiconductor device in which a slew rate variance is small despite an environmental change and a slew rate can be easily controlled. The output driver includes a main driver for driving an output terminal, a delay unit for co... | 01/08/2008 |
