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| Number | Title | Issue Date |
| 8188762 | Controlling dynamic selection of on-die termination A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply ... | 05/29/2012 |
| 8179158 | Printed circuit board having a termination of a T-shaped signal line Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the su... | 05/15/2012 |
| 8174286 | Transceiver circuits A transceiver circuit supports a bidirectional mode and the bidirectional transceiver circuit is signal-compatible with JEDEC SSTL 2. A differential transceiver circuit supports a bidirectional mode and is also signal-compatible with JEDEC SSTL 2. Finally, transceiv... | 05/08/2012 |
| 8169232 | Apparatus and method for generating resistance calibration code in semiconductor integrated circuit A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time co... | 05/01/2012 |
| 8169233 | Programming of DIMM termination resistance values Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the p... | 05/01/2012 |
| 8164358 | Transceiver for single ended communication with low EMI A cable driver (301) for driving a single ended transmission medium such as a coaxial cable (115) comprising a core (120) and a shield (121) comprises a differential driver (104, 377) comprising a first output (151) for putt... | 04/24/2012 |
| 8159262 | Impedance compensation in a buffer circuit A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The mon... | 04/17/2012 |
| 8159261 | Semiconductor circuit A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of th... | 04/17/2012 |
| 8154318 | Signal transceiver apparatus and system A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver w... | 04/10/2012 |
| 8149015 | Transceiver system, semiconductor device thereof, and data transceiving method of the same A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to t... | 04/03/2012 |
| 8149014 | I/O driver for integrated circuit with output impedance control An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for l... | 04/03/2012 |
| 8143912 | Impedance adjustment circuit for adjusting terminal resistance and related method An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a contr... | 03/27/2012 |
| 8138785 | Reduced power output buffer A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a pl... | 03/20/2012 |
| 8134385 | Split cascode line amplifier for current-mode signal transmission Current-mode transmission is implemented in a cascode amplifier by splitting a cascode circuit into a front end and a back end to ensure wideband current-mode transmission of an audio signal. A transmission cable is located between the high impedance output of the f... | 03/13/2012 |
| 8134386 | Hybrid frequency compensation network Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction ... | 03/13/2012 |
| 8130010 | Signal lines with internal and external termination Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impeda... | 03/06/2012 |
| 8125241 | Automatic de-emphasis setting for driving capacitive backplane In described embodiments, automatic de-emphasis setting is provided for driving a capacitive backplane. Line impedance and line length of a transmission (TX) device are measured that form a load impedance of a driver. For some exemplary embodiments, the line impedan... | 02/28/2012 |
| 8120381 | Impedance adjusting device An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface n... | 02/21/2012 |
| 8111085 | Semiconductor integrated circuit, semiconductor storage device and impedance adjustment method It is desired to reduce the current consumption of an autonomous impedance adjustment circuit. The semiconductor integrated circuit according to the present invention stops the change in the drive capability of a driver correspondingly to the output (count data) of ... | 02/07/2012 |
| 8111084 | Impedance calibration circuit and semiconductor apparatus using the same An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured ... | 02/07/2012 |
| 8106677 | Signal transmitting device suited to fast signal transmission A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting ... | 01/31/2012 |
| 8106676 | Semiconductor device A semiconductor device includes a signal generating circuit that generates an impedance adjustment command signal which indicates at least one of initiation and termination of an impedance adjustment. The semiconductor device outputs an output signal in synchronism ... | 01/31/2012 |
| 8102186 | Semiconductor integrated circuit with first and second transmitter-receivers Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a... | 01/24/2012 |
| 8089298 | Integrated circuit device with dynamically selected on-die termination In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination ... | 01/03/2012 |
| 8085061 | Output circuit of semiconductor device An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and a... | 12/27/2011 |
| 8085062 | Configurable bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termi... | 12/27/2011 |
| 8076954 | Memory control circuit, memory control method, and integrated circuit Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for... | 12/13/2011 |
| 8072235 | Integrated circuit with configurable on-die termination Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, ... | 12/06/2011 |
| 8067956 | Apparatus and method for calibrating on-die termination in semiconductor memory device An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the com... | 11/29/2011 |
| 8067957 | USB 2.0 HS voltage-mode transmitter with tuned termination resistance A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver ... | 11/29/2011 |
| 8063658 | Termination circuit for on-die termination In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor ... | 11/22/2011 |
| 8058895 | Single-resistor static programming circuits and methods A method of programming an integrated circuit to operate in a selected operating mode includes assigning different resistance values to correspond to different operating modes of the integrated circuit, wherein the different resistance values are non-zero finite val... | 11/15/2011 |
| 8054100 | Line transceiver apparatus for multiple transmission standards A line transceiver apparatus for multiple transmission standards including a operational amplifier (OP-AMP), a transformer unit, a first variable resistor unit to a sixth variable resistor unit, and a variable resistor control unit is provided. The first resistor an... | 11/08/2011 |
| 8049530 | Output impedance calibration circuit with multiple output driver models A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the... | 11/01/2011 |
| 8044680 | Semiconductor memory device and on-die termination circuit An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a... | 10/25/2011 |
| 8044679 | On-die termination control circuit of semiconductor memory device On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transf... | 10/25/2011 |
| 8040150 | Impedance adjustment circuit An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circu... | 10/18/2011 |
| 8035412 | On-die termination latency clock control circuit and method of controlling the on-die termination latency clock A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal in... | 10/11/2011 |
| 8035413 | Dynamic impedance control for input/output buffers A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode... | 10/11/2011 |
| 8030961 | Semiconductor integrated circuit A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltag... | 10/04/2011 |
