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| Number | Title | Issue Date |
| 8149013 | High speed integrated circuit A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's output... | 04/03/2012 |
| 8115509 | Semiconductor integrated circuit for reducing crosstalk A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is ... | 02/14/2012 |
| 7982490 | Semiconductor integrated circuit Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-s... | 07/19/2011 |
| 7952381 | Semiconductor device A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage... | 05/31/2011 |
| 7949988 | Layout circuit having a combined tie cell A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard ... | 05/24/2011 |
| 7940076 | Local interconnect network transceiver driver Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input ... | 05/10/2011 |
| 7928756 | Method and system for reducing I/O noise and power In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low... | 04/19/2011 |
| 7906985 | Semiconductor device A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, ... | 03/15/2011 |
| 7872491 | Noise filter circuit, dead time circuit, delay circuit, noise filter method, dead time method, delay method, thermal head driver, and electronic instrument A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first in... | 01/18/2011 |
| 7872492 | Triple latch flip flop system and method A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down no... | 01/18/2011 |
| 7830167 | Pre-emphasis circuit A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The tra... | 11/09/2010 |
| 7821289 | Data output driving circuit and method for controlling slew rate thereof A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control... | 10/26/2010 |
| 7786751 | Differential signaling system and method of controlling skew between signal lines thereof The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitte... | 08/31/2010 |
| 7772875 | Input/output circuit for evaluating delay An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the... | 08/10/2010 |
| 7768296 | Electronic device and method A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supple... | 08/03/2010 |
| 7755382 | Current limited voltage supply A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through t... | 07/13/2010 |
| 7705626 | Design structure to eliminate step response power supply perturbation A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header... | 04/27/2010 |
| 7692445 | Output buffer circuit and differential output buffer circuit, and transmission method In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a t... | 04/06/2010 |
| 7679395 | Low-loss impedance-matched source-follower for repeating or switching signals on a high speed link Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit ... | 03/16/2010 |
| 7679396 | High speed integrated circuit Method and apparatus are disclosed for implementing low noise circuits. The method includes providing a first subcircuit and a second subcircuit, where the first subcircuit and the second subcircuit include substantially same circuit elements and have substantially ... | 03/16/2010 |
| 7538572 | Off-chip driver apparatus, systems, and methods Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to ... | 05/26/2009 |
| 7514953 | Adjustable transistor body bias generation circuitry with latch-up prevention An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circ... | 04/07/2009 |
| 7511528 | Device and method to eliminate step response power supply perturbation A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary heade... | 03/31/2009 |
| 7511529 | Reduced area active above-ground and below-supply noise suppression circuits A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and genera... | 03/31/2009 |
| 7495466 | Triple latch flip flop system and method A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down no... | 02/24/2009 |
| 7477068 | System for reducing cross-talk induced source synchronous bus clock jitter A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. ... | 01/13/2009 |
| 7456649 | Open drain output circuit An open drain output circuit for use as an I2C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually... | 11/25/2008 |
| 7449913 | Pre-driver having slew-rate and crowbar-current controls for a CMOS output buffer An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down... | 11/11/2008 |
| 7439759 | Operating long on-chip buses As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to po... | 10/21/2008 |
| 7436201 | Architecture for reducing leakage component in semiconductor devices An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rail... | 10/14/2008 |
| 7432730 | Time based driver output transition (slew) rate compensation Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A ... | 10/07/2008 |
| 7429878 | Apparatus for controlling drive current in semiconductor integrated circuit devices A circuit device for variously controlling a current drive capacity of a semiconductor IC device as required by the user. A circuit device, capable of preventing a semiconductor IC device from failing to drive an external device, preventing an operational speed of t... | 09/30/2008 |
| 7427873 | Systems and methods for current management for digital logic devices Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one... | 09/23/2008 |
| 7423454 | High speed signaling system with adaptive transmit pre-emphasis A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to genera... | 09/09/2008 |
| 7417451 | Leakage power management with NDR isolation devices A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device rai... | 08/26/2008 |
| 7417458 | Gate driving circuit and display apparatus having the same In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-nod... | 08/26/2008 |
| 7411414 | Single-ended output driver buffer Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad... | 08/12/2008 |
| 7408377 | Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding tra... | 08/05/2008 |
| 7394290 | Semiconductor integrated circuit A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion incl... | 07/01/2008 |
| 7382151 | Method for reducing cross-talk induced source synchronous bus clock jitter A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. ... | 06/03/2008 |
