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| Number | Title | Issue Date |
| 7786749 | Programmable integrated circuit having built in test circuit A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of progra... | 08/31/2010 |
| 7772873 | Solid state thermal electric logic A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic... | 08/10/2010 |
| 7768294 | Pulse latch circuit and semiconductor integrated circuit The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a secon... | 08/03/2010 |
| 7750665 | Semiconductor device A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the i... | 07/06/2010 |
| 7728617 | Debug network for a configurable IC Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the con... | 06/01/2010 |
| 7724024 | Semiconductor device with its test time reduced and a test method therefor In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The... | 05/25/2010 |
| 7724023 | Circuit apparatus including removable bond pad extension Embodiments of the invention include an electrical circuit arrangement including a switchably removable bond pad extension test pad that allows improved testing of a corresponding electrical circuit device via enhanced placement of testing probes. The bond pad exten... | 05/25/2010 |
| 7688103 | Cell with fixed output voltage for integrated circuit The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of th... | 03/30/2010 |
| 7683653 | Process and circuit for improving the life duration of field-effect transistors The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tS | 03/23/2010 |
| 7649379 | Reducing mission signal output delay in IC having mission and test modes An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a sm... | 01/19/2010 |
| 7646210 | Method and system for low-power level-sensitive scan design latch with power-gated logic A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gat... | 01/12/2010 |
| 7639036 | Semiconductor integrated circuit A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to ... | 12/29/2009 |
| 7629810 | Input and output circuit Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element ... | 12/08/2009 |
| 7595655 | Retrieving data from a configurable IC Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. I... | 09/29/2009 |
| 7570076 | Segmented programmable capacitor array for improved density and reduced leakage A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328 | 08/04/2009 |
| 7548085 | Random access of user design states in a configurable IC Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a sec... | 06/16/2009 |
| 7518394 | Process monitor vehicle A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memo... | 04/14/2009 |
| 7514951 | Negative voltage noise-free circuit for multi-functional pad A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode circuitry and a test mode internal node, which connects to test mode circu... | 04/07/2009 |
| 7501850 | Scannable limited switch dynamic logic (LSDL) circuit A scannable limited switch dynamic logic (LSDL) circuit including a data input and a data output, a combinational logic circuit in communication with the data input, a pre-charge circuit in communication with the combinational logic circuit, a footer circuit in comm... | 03/10/2009 |
| 7459928 | Cell with fixed output voltage for integrated circuit The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of th... | 12/02/2008 |
| 7453282 | Input and output circuit of an integrated circuit and a method for testing the same An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the p... | 11/18/2008 |
| 7436211 | Transparent latch circuit The present invention provides a transparent latch circuit capable of performing a scan test in general scan design (GSD). In the transparent latch circuit a test signal is at a Low level during normal operation. Since a latch stop circuit outputs a High-level latch... | 10/14/2008 |
| 7436204 | Apparatus and method for determining on die termination modes in memory device For determining an on die termination (ODT) mode in a semiconductor memory device, a first mode determining unit determines whether or not a normal ODT mode is enabled from performing a logic operation on a first set of signals. A second mode determining unit determ... | 10/14/2008 |
| 7423449 | Electronic circuit An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed ... | 09/09/2008 |
| 7411413 | Pulse latch circuit and semiconductor integrated circuit The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a secon... | 08/12/2008 |
| 7405990 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/29/2008 |
| 7403026 | Electronic switching circuit, switching circuit test arrangement and method for determining the operativeness of an electronic switching circuit The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first s... | 07/22/2008 |
| 7397274 | In-system programming of a non-compliant device using multiple interfaces of a PLD In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data fo... | 07/08/2008 |
| 7397709 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/08/2008 |
| 7397269 | Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal input... | 07/08/2008 |
| 7392446 | Test channel usage reduction Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1 through 310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are... | 06/24/2008 |
| 7385312 | Method and apparatus for mode selection for high voltage integrated circuits A method is disclosed to add functionality to a terminal of a high voltage integrated circuit without the penalty of additional high voltage circuitry. The benefit is that alternative modes of operation can be selected for testing, trimming parameters of the integra... | 06/10/2008 |
| 7372760 | Semiconductor device and entry into test mode without use of unnecessary terminal A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal and the second power supply terminal to produce at an output node thereof a signal responsive to a differen... | 05/13/2008 |
| 7372294 | On-die termination apparatus An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding uni... | 05/13/2008 |
| 7373538 | Method for determining interconnect line performance within an integrated circuit A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated ... | 05/13/2008 |
| 7372302 | High speed, out-of-band differential pin driver A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source a... | 05/13/2008 |
| 7373567 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented... | 05/13/2008 |
| 7362093 | IC selectively connecting logic and bypass conductors between opposing pads In a functional mode, the functional core logic of a die is connected to the input and output pads and the die performs its intended function. In a bypass mode, the input and output buffers of the functional core logic are disabled and pad sites of corresponding pos... | 04/22/2008 |
| 7363545 | System and method for overcoming download cable bottlenecks during programming of integrated circuit devices A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the compu... | 04/22/2008 |
| 7363564 | Method and apparatus for securing communications ports in an electronic device An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordanc... | 04/22/2008 |
