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Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 8174285 | Component provided with an integrated circuit comprising a cryptorocessor and method of installation thereof In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar trans... | 05/08/2012 |
| 7944230 | Methodology and apparatus for reduction of soft errors in logic circuits The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when ... | 05/17/2011 |
| 7852108 | Single event upset resilient programmable interconnect In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an in... | 12/14/2010 |
| 7804320 | Methodology and apparatus for reduction of soft errors in logic circuits The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when ... | 09/28/2010 |
| 7501849 | Latch-up prevention circuitry for integrated circuits with transistor body biasing An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Bo... | 03/10/2009 |
| 7427871 | Fault tolerant integrated circuit architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element inter... | 09/23/2008 |
| 7427872 | Asynchronous coupling and decoupling of chips In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the firs... | 09/23/2008 |
| 7245159 | Protecting one-hot logic against short-circuits during power-on A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high sp... | 07/17/2007 |
| 7236034 | Self correcting scheme to match pull up and pull down devices The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having a... | 06/26/2007 |
| 7212027 | Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted fro... | 05/01/2007 |
| 7202725 | Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the ... | 04/10/2007 |
| 7155695 | Signal shielding technique using active shields for non-interacting driver design A technique for actively shielding a signal such that a signal driver of the signal only participates in discharge events is provided. Because the signal driver only participates in discharge events, the signal driver is non-interacting with respect to other driver ... | 12/26/2006 |
| 7155360 | Process variation detector and process variation detecting method A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a pre... | 12/26/2006 |
| 7134354 | Display for process transmitter A transmitter for use in a process control system for monitoring an industrial process includes a housing having a top and a bottom and a height extending therebetween. A parallelogram display is mounted to the housing. Sides of the parallelogram display are arrange... | 11/14/2006 |
| 7130175 | Monolithic integratable circuit arrangement for protection against a transient voltage At least one or more terminals of an integrated circuit, such as a low- or high-side driver stage, are protected against transient or over-voltages by two pairs of diodes. A first pair of diodes includes a regular diode (D1 or D1′) and a Zener-diode (ZD1 or ZD1′... | 10/31/2006 |
| 7109883 | Low power physical layer for a bus in an industrial transmitter A process variable transmitter connects a serial bus to an accessory load. A supply limiter circuit provides a first supply current limit and provides a stored energy output. A recessive driver circuit draws a drive current from the stored energy output and couples ... | 09/19/2006 |
| 7064574 | PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets Structures and methods of reducing the susceptibility of programmable logic device (PLD) configuration memory cells to single event upsets (SEUs) by selectively adding metal-to-metal capacitors thereto. By adding capacitance to storage nodes in a memory cell, the su... | 06/20/2006 |
| 7061735 | Semiconductor device A semiconductor device has an electrostatic protection diode in a signal input portion thereof and is accompanied by a parasitic transistor between the diode and an output control transistor. The semiconductor device further has a dummy transistor that is formed clo... | 06/13/2006 |
| 7036381 | High temperature pressure transmitter assembly A pressure transmitter assembly for measuring a pressure of a process fluid includes an isolation diaphragm assembly. A pressure sensor is spaced apart from the isolation diaphragm assembly to provide thermal isolation. A conduit extends from the isolation diaphragm... | 05/02/2006 |
| 7019550 | Leakage testing for differential signal transceiver A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the... | 03/28/2006 |
| 7006005 | Adapter pod for use in medical perfusion system An adapter pod for use in a medical perfusion system having a data communications network with a plurality of connection points each having a substantially identical network connector. The adapter pod includes a housing and a common connector associated with the hou... | 02/28/2006 |
| 6993082 | Station and method for operating a CAN communication line A CAN communication line is operated whilst detecting a ground level shift on the communication line through storing a data element indicative for the shift. In particular, a current line voltage level is compared to a standard level, and a thresholded version of th... | 01/31/2006 |
| 6978434 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying “W/H | 12/20/2005 |
| 6922073 | Circuit configuration for signal balancing in antiphase bus drivers A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an an... | 07/26/2005 |
| 6917221 | Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as a... | 07/12/2005 |
| 6906567 | Method and structure for dynamic slew-rate control using capacitive elements A method and structure for providing dynamic control of a slew rate of an electronic circuit. The structure has a signal line that is coupled to a number of capacitive elements that may be selectively switched in or out of the electronic circuit in order to provide ... | 06/14/2005 |
| 6903571 | Programmable systems and devices with multiplexer circuits providing enhanced capabilities for triple modular redundancy Programmable systems and devices that include programmable multiplexers designed to minimize the impact of single event upsets (SEUs) on triple modular redundancy (TMR) circuits. In a programmable routing multiplexer, each path through the multiplexer is controlled ... | 06/07/2005 |
| 6842042 | Global chip interconnect A global interconnect distribution system is disclosed. The global interconnect distribution system includes a global interconnect cell capable of producing at least two substantially identical output signals, and a global interconnect coupled to the cell for carryi... | 01/11/2005 |
| 6810511 | Method of designing active region pattern with shift dummy pattern A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a f... | 10/26/2004 |
| 6806738 | Semiconductor circuit device capable of high speed decoding An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real addr... | 10/19/2004 |
| 6801051 | System and method for providing capacitive spare fill cells in an integrated circuit A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one spare fill cell disposed in at least one portion of the processor that i... | 10/05/2004 |
| 6744273 | Semiconductor device capable of reducing noise to signal line A semiconductor device includes a signal line and two adjacent wirings formed on a first substrate layer, an adjacent wiring formed on a second substrate layer, and an adjacent wiring formed on a third substrate layer. A logical level on the signal line is set const... | 06/01/2004 |
| 6653857 | Increasing implicit decoupling capacitance using asymmetric shieldings An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetri... | 11/25/2003 |
| 6577178 | Transient gate tunneling current control A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxide... | 06/10/2003 |
| 6456117 | Shield circuit and integrated circuit in which the shield circuit is used A shield circuit includes shielding wires and a shielding wire driving circuit, the shielding wires being provided along a target wire that requires shielding, and the shielding wire driving circuit driving the shielding wires with a logical value corresp... | 09/24/2002 |
| 6288572 | Method and apparatus for reducing leakage in dynamic silicon-on-insulator logic circuits A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input... | 09/11/2001 |
| 6285208 | Activation speed of signal wiring line in semiconductor integrated circuit A semiconductor integrated circuit includes a plurality of signal wiring lines, and a plurality of shield wiring lines, each of which is arranged between adjacent two of the plurality of signal wiring lines. An interference preventing section is connected... | 09/04/2001 |
| 6188247 | Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a conte... | 02/13/2001 |
| 6124735 | Method and apparatus for a N-nary logic circuit using capacitance isolation The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate... | 09/26/2000 |
| 6094072 | Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect tra... | 07/25/2000 |
