Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 6480019 | Multiple voted logic cell testable by a scan chain and system and method of testing the same A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and gene... | 11/12/2002 |
| 6476643 | Asynchronous circuit for detecting and correcting soft error and implementation method thereof A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal d... | 11/05/2002 |
| 6448806 | Circuit for providing a logical output signal in accordance with crossing points of differential signals A circuit provides an output signal in accordance with crossing points of a differential signal, which includes a normal input signal and a complementary input signal. The circuit includes a first amplifier for amplifying a first signal difference between... | 09/10/2002 |
| 6420896 | Semiconductor integrated circuit To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data input... | 07/16/2002 |
| 6396315 | Voltage clamp for a failsafe buffer A voltage clamp for a failsafe buffer used in connection with an electronic device. The voltage clamp clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, and present a high impedance when the electr... | 05/28/2002 |
| 6381506 | Fail-safe microprocessor-based control and monitoring of electrical devices A fail-safe microprocessor-based system and method permits the controlling and monitoring of electrical devices for use in fail-safe interfacing of electrical devices to microprocessor-based control equipment in applications that are highly safety-critica... | 04/30/2002 |
| 6320406 | Methods and apparatus for a terminated fail-safe circuit An active fail-safe method and apparatus for a LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of a valid input signal; i.... | 11/20/2001 |
| 6316956 | Multiple redundant reliability enhancement method for integrated circuits and transistors In a fault-tolerant integrated power circuit, a plurality of power transistors, each having a power source electrically coupled to a common source line, a power gate and a power drain electrically coupled to a common drain line, is capable of driving a po... | 11/13/2001 |
| 6304112 | Integrated circuit provided with a fail-safe mode An integrated circuit provided with an improved fail-safe mode.... | 10/16/2001 |
| 6300787 | System and method for observing information transmitted between two integrated circuits A system and method for observing bi-directional information transmitted between two integrated circuits is disclosed. The bi-directional information is transmitted on first and second communication links between a first and a second integrated circuit. T... | 10/09/2001 |
| 6288577 | Active fail-safe detect circuit for differential receiver A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V- differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as ... | 09/11/2001 |
| 6288572 | Method and apparatus for reducing leakage in dynamic silicon-on-insulator logic circuits A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input... | 09/11/2001 |
| 6271677 | Semiconductor integrated circuit and method for testing the semiconductor integrated circuit A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a t... | 08/07/2001 |
| 6188247 | Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a conte... | 02/13/2001 |
| 6184700 | Fail safe buffer capable of operating with a mixed voltage core A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in ... | 02/06/2001 |
| 6175938 | Scheme for the reduction of extra standby current induced by process defects A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the repairing process, the fuses connected with the pull-transis... | 01/16/2001 |
| 6104211 | System for preventing radiation failures in programmable logic devices A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit inc... | 08/15/2000 |
| 5789943 | V.35 network terminator A V.35 compliant driver is disclosed. The driver has three operational modes: OFF, low power (approximately 1/3 full power), and full power. The driver is placed in an appropriate mode based on conditions sensed at driver outputs. More particularly, the d... | 08/04/1998 |
| 5781058 | Totem pole driver with cross conduction protection and default low impedance state output A totem pole driver with cross conductive protection and default low impedance state output employs a totem pole output formed by top and bottom output transistors. A first circuit path switches the bottom output transistor on or off in response to a swit... | 07/14/1998 |
| 5619643 | Circuit for detecting a fault state in a clock signal for microprocessor electronic devices A circuit for generation of a reset signal in an electronic device, of the type comprising a microprocessor interlocked with a circuit generating a clock signal and memories of both the volatile type and the non-volatile type, is capable of detecting a st... | 04/08/1997 |
| 5550486 | Circuit and method for providing a known logic state at insufficient supply voltage A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected... | 08/27/1996 |
| 5450024 | ECL to CMOS signal converter circuit including toggle-fault detection An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit shif... | 09/12/1995 |
| 5442303 | Electromagnetically coupled fail-safe logic circuit A fail-safe logic circuit employs a transformer (T) and a level tester (1). The transformer receives input signals each representing a binary logic variable and provides the sum of magnetic flux based on the input signals. The level tester tests the level... | 08/15/1995 |
| 5418472 | Input level detection circuit An apparatus for activating a dual-mode logic device is provided. The apparatus monitors a parameter of an input signal of the logic device. If the parameter falls outside of predetermined parametric ranges, the apparatus activates the logic device. In th... | 05/23/1995 |
| 5374861 | Differential termination network for differential transmitters and receivers A system of terminating a differential transmission line is described, where the differential transmitter and differential receiver are supplied by different power sources. The termination circuit comprises an unbalanced voltage divider pair, a connection... | 12/20/1994 |
| 5369311 | Clock generator control circuit A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense le... | 11/29/1994 |
| 5365117 | Logic gates having fast logic signal paths through switchable capacitors Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast si... | 11/15/1994 |
| 5357151 | Intrinsically safe logic and-circuit having two inputs A logic AND circuit comprises, in a cascade arrangement, a threshold oscillator having a power supply input connected to a first circuit input and a clamping amplifier providing an output signal only when simultaneously the voltage on a second circuit inp... | 10/18/1994 |
| 5220211 | High speed bus transceiver with fault tolerant design for hot pluggable applications A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which... | 06/15/1993 |
| 5194853 | Scanning circuit A scanning circuit for successively scanning a plural number of capacitive loads comprising: a delay circuit 101 for delaying a supplied pulse signal from a previous stage in accordance with a first clock signal; a switching transistor 102 which is contro... | 03/16/1993 |
| 5149990 | Semiconductor device for preventing malfunction caused by a noise A semiconductor device for absorbing a noise comprises a first and second buffer. The first and second buffers receive an external signal having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first... | 09/22/1992 |
| 5140594 | Method and device for avoiding latent errors in a logic network for majority selection of binary signals A method for avoiding latent errors in a logic network for majority selection of binary signals in a triplicated system. Errors which result from errors or faults in one of two or more parallel-connected transistors of one or more separate logic devices i... | 08/18/1992 |
| 5126596 | Transmission gate having a pass transistor with feedback A CMOS transmission gate circuit having a pass transistor and a feedback transistor is coupled across a logic gate. The pass transistor is responsive to a control signal for passing a logic signal. The feedback transistor aids the pass transistor in passi... | 06/30/1992 |
| 5111073 | Wafer-scale semiconductor device having fail-safe circuit A wafer-scale semiconductor memory device includes a wafer, and a plurality of memory chips formed on the wafer. The memory chips contain a memory chip which includes a storage circuit, and a switching transistor which selectively connects the storage cir... | 05/05/1992 |
| 5065047 | Digital circuit including fail-safe circuit A digital circuit including a processor operated in synchronization with a clock signal to output a control signal to be fed to an actuator, in which a converter converts a period of frequency of the clock signal to an analog voltage value, and a comparat... | 11/12/1991 |
| 5031180 | Triple redundant fault-tolerant register A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in paralle... | 07/09/1991 |
| 5025178 | Fault-resistant solid-state line driver A fault-resistant, solid-state line driver having a pair of P-type transistors in series between a bus output and a voltage source, a pair of N-type transistors in series between the bus output and a connection to ground, and a pair of input lines, one of... | 06/18/1991 |
| 5021683 | Circuit arrangement comprising two parallel branches for transmitting a binary signal A circuit arrangement for transmitting in an undisturbed manner a binary signal through two parallel branches even in case of breakdown, failure or interruption of operating voltages of individual components of a branch, and also to enable a disturbance-f... | 06/04/1991 |
| 5015875 | Toggle-free scan flip-flop A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master la... | 05/14/1991 |
| 4983861 | Semiconductor integrated circuit with an input buffer circuit for preventing false operation caused by power noise A semiconductor integrated circuit comprises a first input circuit for generating an internal chip enable signal in response to a chip enable signal externally applied; and a second input circuit for supplying to an internal circuit a signal corresponding... | 01/08/1991 |
