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| Number | Title | Issue Date |
| 7135885 | Dynamically adjustable signal detector A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, pea... | 11/14/2006 |
| 7132857 | High speed receiver with wide input voltage range A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is cou... | 11/07/2006 |
| 7123458 | Method and circuit arrangement for protecting an electric motor from an overload A method and a circuit for protecting an electric motor and/or its trigger circuit against overload in the emergency-operation mode in a motor vehicle direct-current fan motor operated by means of pulse width modulation, in which the trigger circuit is designed as a... | 10/17/2006 |
| 7103609 | System and method for analyzing usage patterns in information aggregates System and method for evaluating an information aggregate. A metrics database stores document indicia including document attributes, associated persons and usage metrics. A query engine collects a plurality of documents having non-unique values on a shared attribute... | 09/05/2006 |
| 7075328 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the rou... | 07/11/2006 |
| 7042251 | Multi-function differential logic gate A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/09/2006 |
| 7023259 | High voltage switch with no latch-up hazards The present invention discloses a method and system of generating and delivering a high voltage signal without latch-up hazards and without incurring a voltage drop due to the threshold of the switching element. The utilization of NMOS elements when switching a high... | 04/04/2006 |
| 6995601 | Fuse state detection circuit A fuse state detection circuit (300) has a reference circuit part (302, 302′) and a fuse detection circuit part (308, 308′), the reference circuit part (302, 302′) having a fuse (304, 304′) identical to a fuse (306, 306 | 02/07/2006 |
| 6996795 | Data processing in digital systems A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data bu... | 02/07/2006 |
| 6980023 | Dynamically adjustable signal detector A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, pea... | 12/27/2005 |
| 6965250 | Reduced delay power fail-safe circuit An improved power fail-safe has an effective maximum delay of two gate delays from an input operably powered by a first power supply to a first and a second output operably powered by a second power supply. The first and second outputs have predetermined values duri... | 11/15/2005 |
| 6960930 | Method and apparatus for determining the minimum or maximum switching activity of a digital circuit In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined according to the invention on the basis of a model of the digital circuit whether there is a disproving ... | 11/01/2005 |
| 6958622 | Scan-mode indication technique for an integrated circuit An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an integrated circuit is utilized for indicating entry of a digital block of ... | 10/25/2005 |
| 6954083 | Circuit for detection of hardware faults due to temporary power supply fluctuations Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embod... | 10/11/2005 |
| 6949965 | Low voltage pull-down circuit A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be easily pulled-up to a logic HIGH voltage, for example, by simpl... | 09/27/2005 |
| 6943591 | Apparatus and method for detecting a fault condition in a common-mode signal The invention is directed to an apparatus and a method for generating a fault detection signal when a differential signal is in a fault condition. The fault condition arises when the data transmission path in a differential signaling device is either open, shorted, ... | 09/13/2005 |
| 6937053 | Single event hardening of null convention logic circuits A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the... | 08/30/2005 |
| 6933745 | Bus network interface A system and method for transmitting data includes one or more transmitters connected to each of at least one bus data line via open-driver bus data line drivers, and one or more receivers. In a preferred embodiment, the devices are interconnected by a parallel inte... | 08/23/2005 |
| 6927599 | Failsafe for differential circuit based on current sense scheme A system and method are described for receiving differential currents in a current mode circuit. When conditions occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diod... | 08/09/2005 |
| 6928132 | Methods and apparatus for operating a system A method for operating a system having a plurality of modes and interlocks between the modes is provided. The method includes operating the system in a first mode and switching the system to a second mode without going to a standby mode. ... | 08/09/2005 |
| 6815978 | Single clock source for plural scan capture chains A clock signal is applied to a clock pin of an integrated circuit. The clock signal is coupled from the clock pin to a first scan chain in a first time period without coupling the clock signal to a second scan chain during the first time period. The clock signal is ... | 11/09/2004 |
| 6791362 | System level hardening of asynchronous combinational logic A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an ... | 09/14/2004 |
| 6788097 | Security improvements for programmable devices A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is coupled to an observation pin to allow for external observation of the powe... | 09/07/2004 |
| 6781456 | Failsafe differential amplifier circuit Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is detected and signaled. The output signal form the fail safe circuitry is h... | 08/24/2004 |
| 6756808 | Clock edge detection circuit The clock edge detection circuit is equipped with a first delay circuit 11 that delays a first clock signal and outputs a first delay clock signal, a second delay circuit 21 that delays a second clock signal and outputs a second delay clock signal, a f... | 06/29/2004 |
| 6731131 | Circuit for an electronic semiconductor module It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is additionally provided, which is connected to the n inputs on an input side and... | 05/04/2004 |
| 6720793 | Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDS, a single event upset can short together two module output signals and re... | 04/13/2004 |
| 6719388 | Fail-safe circuit for dynamic smartpower integrated circuits A method and Apparatus for protection of semiconductor micromechanical devices that use circuits with dynamic logic addressing is disclosed. In one exemplary embodiment of the invention, a fail-safe circuit is provided for an ink jet print head integrated circuit wh... | 04/13/2004 |
| 6696851 | Reception line break detection apparatus A reception line break detection apparatus includes a transmission-side line drive, a reception line, a switching element, and a reception-side line receiver receiving signals transmitted from the transmission-side line drive through the reception line. T... | 02/24/2004 |
| 6674319 | Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines eq... | 01/06/2004 |
| 6670823 | Detecting counter contents for time-critical applications An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes logical states. In one implementation, an additional bit is... | 12/30/2003 |
| 6624654 | Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the interconnect lines of the PLD, two routed nodes are separated from ea... | 09/23/2003 |
| 6593801 | Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines A shunt resistor between a pair of differential lines equ... | 07/15/2003 |
| 6570401 | Dual rail power supply sequence tolerant off-chip driver The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme... | 05/27/2003 |
| 6563335 | Semiconductor device and test method therefor A semiconductor device and a test method therefor can perform delay evaluation without depending on a chip size and a measuring unit. An input I/O circuit and an output I/O circuit are disposed on a semiconductor chip of a semiconductor device. A test cel... | 05/13/2003 |
| 6563322 | Method and apparatus for detecting open circuit fault condition in a common-mode signal The present invention relates to an apparatus and a method for detecting an open circuit fault condition in a differential signal, and generating a fault detection signal. An open circuit fault condition is detected by employing weak current sources to pu... | 05/13/2003 |
| 6529032 | Methods and apparatus for full I/O functionality and blocking of backdrive current An input/output (I/O) port designed for electrical interconnection with multiple similar ports includes an input read circuit, an output drive circuit, and a circuit to control the port for input or output mode by electrically disconnecting the output dri... | 03/04/2003 |
| 6522168 | Interface latch for data level transfer An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the... | 02/18/2003 |
| 6504410 | Fault tolerant storage cell A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated... | 01/07/2003 |
| 6486695 | Protecting unit A protecting unit is provided. The protecting unit can prevent accidents from occurring that become problems when data are transmitted due to for instance LVDS and for instance laser light is emitted based on the data. The protecting unit is applied in an... | 11/26/2002 |
