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| Number | Title | Issue Date |
| 7936186 | Method and apparatus for correcting duty cycle via current mode logic to CMOS converter Embodiments of the invention relate generally to the field of duty cycle correction, and more particularly to method and apparatus for correcting duty cycle of a CMOS level signal when converted from a Current-Mode-Logic (CML) to a CMOS level signal via a CML to CMO... | 05/03/2011 |
| 7821300 | System and method for converting between CML signal logic families A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal... | 10/26/2010 |
| 7564270 | Differential output driver A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative comm... | 07/21/2009 |
| 7498847 | Output driver that operates both in a differential mode and in a single mode An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mo... | 03/03/2009 |
| 7474127 | Signal converter According to one embodiment of the invention, a method for receiving a first signal in a first plurality of switching elements from a second plurality of switching elements, receiving a second signal in second plurality of switching elements from first plurality of ... | 01/06/2009 |
| 7429874 | Replica bias circuit Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors ... | 09/30/2008 |
| 7425847 | Input buffer with optimal biasing and method thereof A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averag... | 09/16/2008 |
| 7408384 | Drive circuit of computer system for driving a mode indicator A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to... | 08/05/2008 |
| 7397270 | Dynamically-adjustable differential output drivers Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuit... | 07/08/2008 |
| 7394283 | CML to CMOS signal converter A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode referenc... | 07/01/2008 |
| 7385426 | Low current offset integrator with signal independent low input capacitance buffer circuit A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transcon... | 06/10/2008 |
| 7355451 | Common-mode shifting circuit for CML buffers A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tendi... | 04/08/2008 |
| 7307446 | Integrated circuit output driver circuitry with programmable preemphasis Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O ci... | 12/11/2007 |
| 7301371 | Transmitter of a semiconductor device Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a con... | 11/27/2007 |
| 7292069 | Locally asynchronous, block-level synchronous, configurable logic blocks with sub-threshold analog circuits Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed ... | 11/06/2007 |
| 7288971 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 10/30/2007 |
| 7285987 | Self DC-bias high frequency logic gate, high frequency NAND gate and high frequency NOR gate A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupl... | 10/23/2007 |
| 7253663 | Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switc... | 08/07/2007 |
| 7242249 | Peaking transmission line receiver for logic signals A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a hig... | 07/10/2007 |
| 7224189 | AC/DC coupling input network with low-power common-mode correction for current-mode-logic drivers An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator ... | 05/29/2007 |
| 7218145 | Level conversion circuit An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit... | 05/15/2007 |
| 7215170 | Low voltage logic circuit with set and/or reset functionality A low voltage logic circuit with asynchronous SET and/or RESET functions is described herein. The low voltage logic circuit may be primarily used in forming low voltage flip-flop circuits, but may also be used to form multiplexers and other logic configurations. The... | 05/08/2007 |
| 7215156 | Differential signal driver having complimentary and current-aided pre-emphasis A differential voltage signal (LVDS) driver circuit and/or a Current Mode Logic (CML) driver circuit. The circuit includes two current switches, each coupled to a corresponding input node. In a complementary manner, when a differential signal is applied across the i... | 05/08/2007 |
| 7205796 | AND circuit An AND circuit is provided, which has a first differential pair including a first transistor and a second transistor, to which a first input differential signal is inputted, a second differential pair including a third transistor and a fourth transistor, to which a ... | 04/17/2007 |
| 7202706 | Systems and methods for actively-peaked current-mode logic A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND g... | 04/10/2007 |
| 7202703 | Single stage level restore circuit with hold functionality A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge cloc... | 04/10/2007 |
| 7196551 | Current mode logic buffer Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltag... | 03/27/2007 |
| 7187212 | System and method for providing a fast turn on bias circuit for current mode logic transmitters A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacit... | 03/06/2007 |
| 7187208 | Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchroni... | 03/06/2007 |
| 7187207 | Leakage balancing transistor for jitter reduction in CML to CMOS converters The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled ... | 03/06/2007 |
| 7183805 | Method and apparatus for multi-mode driver Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted t... | 02/27/2007 |
| 7183809 | Current mode transmitter capable of canceling channel charge error A current mode transmitter includes a first sink current path, through which a current flows from an output port according to a first bias voltage, a charge error canceller, which supplies a current from a high power supply voltage to a current control port in respo... | 02/27/2007 |
| 7183804 | Process and device for outputting a digital signal To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a r... | 02/27/2007 |
| 7180333 | Current mode logic driver that employs a level shifting mechanism Circuit for providing drive signal waveforms. The circuit includes a current mode logic (CML) driver that includes a common mode voltage (VCM), an output node and a complementary output node. The circuit also has a level shifting mechanism that is coupled to the CML... | 02/20/2007 |
| 7145366 | Electronic circuit with a differential pair of transistors and logic gate comprising such a circuit An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to acce... | 12/05/2006 |
| 7138822 | Integrated circuit and method of improving signal integrity An integrated circuit comprising a first output stage circuit and a second output stage circuit that share common input terminals and an output terminal of the first and second output stage circuits being selectably coupled between the input terminals and the output... | 11/21/2006 |
| 7132857 | High speed receiver with wide input voltage range A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is cou... | 11/07/2006 |
| 7132848 | Power management circuit A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of da... | 11/07/2006 |
| 7129756 | Semiconductor integrated circuit A semiconductor integrated circuit with stabilized amplitude and offset potential of output signals comprising an output circuit including plural transistors supplied with differential signals, for performing switching operation. A first transistor is connected betw... | 10/31/2006 |
| 7109743 | Integrated circuit output driver circuitry with programmable preemphasis Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O ci... | 09/19/2006 |
