Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7330709 | Receiver circuit using nanotube-based switches and logic Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. ... | 02/12/2008 |
| 7330050 | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable ... | 02/12/2008 |
| 7317331 | Reconfigurable IC that has sections running at different reconfiguration rates Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circ... | 01/08/2008 |
| 7216195 | Architecture for managing disk drives Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives c... | 05/08/2007 |
| 7120761 | Multi-port memory based on DRAM core A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports. ... | 10/10/2006 |
| 7106093 | Semiconductor device A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set... | 09/12/2006 |
| 7075846 | Apparatus for interleave and method thereof An apparatus for interleave includes a serial-parallel circuit which transforms a data form of an input data from serial into parallel and which outputs a plurality of parallel data, a first switch circuit which arranges order of the parallel data based on a first c... | 07/11/2006 |
| 6674308 | Low power wired OR A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal lin... | 01/06/2004 |
| 6411128 | Logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like Even input bit lines, a first latch circuit group and a second latch circuit group are provided in a logical circuit. The first latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the eve... | 06/25/2002 |
| 5959482 | Controlled slew rate bus driver circuit having a high impedance state A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connectin... | 09/28/1999 |
| 5828237 | Emitter coupled logic (ECL) gate and method of forming same A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and... | 10/27/1998 |
| 5754823 | Configurable I/O system using logic state arrays A configurable I/O arrangement for a controller has a number of internal and external input/output terminals, each of which are field selected as either an input or an output terminal. Logic functions of the controller are configured for a number of outpu... | 05/19/1998 |
| 5508634 | Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first l... | 04/16/1996 |
| 5459411 | Wired-OR logic circuits each having a constant current source A wired-OR logic circuit has a plurality of logic circuit connected to a common signal line. Each of the plurality of logic circuits includes an output bipolar transistor for outputting a logical output signal to the common signal line, and a constant-cur... | 10/17/1995 |
| 5436572 | Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first l... | 07/25/1995 |
| 5428305 | Differential logic level translator circuit with dual output logic levels selectable by power connector options Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches... | 06/27/1995 |
| 5233239 | ECL circuit with feedback circuitry for increased speed An ECL output circuit comprises a current switching circuit of the differential circuit type including a first transistor having a base connected to receive an input voltage and a second transistor having a base connected to a first reference voltage. A t... | 08/03/1993 |
| 5206547 | High-speed programmable state counter A programmable state counter generates an output signal when a predetermined count sequence matches a programmed input data pattern. A synchronous maximal length shift counter generates 2N -1 unique output states as a predetermined count sequen... | 04/27/1993 |
| 5200651 | Collector dot and circuit A multi-output collector dot AND circuit wherein a logical AND signal can be formed from a pair of adjacent circuits and another logical AND circuit can also be formed from a pair of circuits spaced from each other. The collector dot AND circuit comprises... | 04/06/1993 |
| 5182473 | Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and ... | 01/26/1993 |
| 5170079 | Collector dot and circuit with latched comparator A logic circuit which can operate to form a logic AND signal of a predetermined voltage level in accordance with a potential difference between a plurality of input signals using a collector dot AND circuit and a latched comparator circuit without the nec... | 12/08/1992 |
| 5162677 | ECL to CMOS level conversion circuit A level conversion circuit has an input buffer circuit which includes bipolar transistors and a complementary type inverter circuit which includes a P-channel first field effect transistor and an N-channel second field effect transistor. An input signal h... | 11/10/1992 |
| 5107145 | High speed current mode logic circuit with constant logic level current A collector-dotted current-mode logic circuit which includes a plurality of current-mode logic circuits each containing a first and a second transistors, where the collectors of the first transists and the collectors of the second transistors are respecti... | 04/21/1992 |
| 5075574 | Differential cascode current switch (DCCS) logic circuit family with input diodes The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) c... | 12/24/1991 |
| 4987318 | High level clamp driver for wire-or buses The drivers of a bus are provided with an internal positive voltage clamp, which insures that large positive voltage waves will not be launched down the bus. By increasing the output conductance of the driver when larger than desired voltage is detected a... | 01/22/1991 |
| 4948991 | Load controlled ECL transient driver An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a ... | 08/14/1990 |
| 4942316 | Cascode logic circuit including a positive level shift at the input of the top logic stage A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35... | 07/17/1990 |
| 4808855 | Distributed precharge wire-or bus A plurality of bus-coupler circuits (14) are connected to a bus wire (10) at different points (12) along its length. Each bus-coupler circuit (14) includes a conventional bus driver (22) which may, for example, comprise a relatively large transistor, but ... | 02/28/1989 |
| 4789797 | Temperature-compensated interface circuit between "OR-tied" connection of a PLA device and a TTL output buffer An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circ... | 12/06/1988 |
| 4760289 | Two-level differential cascode current switch masterslice A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite ... | 07/26/1988 |
| 4721867 | High speed logic gate with simulated open collector output A high speed logic gate is disclosed in which the voltage across the output transistor is clamped by a diode, a current switch transistor, a resistor connected between the diode and the transistor and a resistor connected to ground. A selectable high impe... | 01/26/1988 |
| 4719371 | Differential type gate circuit having control signal input An ordinary differential type gate circuit has two transistors to which complementary inputs are given and which are turned on and off, and complementary type outputs in accordance with the states of the complementary inputs are generated from the collect... | 01/12/1988 |
| 4704549 | CMOS to ECL converter-buffer The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic level... | 11/03/1987 |
| 4697109 | Level converter circuit Herein disclosed is a circuit for converting the logic amplitude of an ECL by logically amplifying a TTL or CMOS so that no substantial dc current flows in the steady state. The level converting circuit comprises: a level-shift circuit for generating a fi... | 09/29/1987 |
| 4691161 | Configurable logic gate array An integrated circuit having an array of logic gates adapted to provide predetermined logic functions on a plurality of input logic signals fed to the gate array and produce such predetermined logic functions as output signals at a plurality of array outp... | 09/01/1987 |
| 4682058 | Three-state logic circuit for wire-ORing to a data bus A three-state logic circuit comprising a logic gate on a semiconductor chip which includes first and second conductors, respective resistors connected to the conductors, terminals for receiving input signals, and transistors for generating complementary o... | 07/21/1987 |
| 4680486 | Combinational logic circuits implemented with inverter function logic Combinational logic circuits are implemented with Inverter Function Logic gates. Such circuits may utilize the logical complement of an input signal in the logical operation performed by the gate without having to use a separate inverter stage or a dual l... | 07/14/1987 |
| 4675553 | Sequential logic circuits implemented with inverter function logic Sequential logic circuits are implemented with inverter function logic gates. In each circuit, level shifted transistor means are utilized in place of the standard reference transistors found in ECL gate circuits so that the complement of at least one of ... | 06/23/1987 |
| 4675552 | Single input/multiple output logic interface circuit having minimized voltage swing A single input/multiple output NOR gate employs a reference voltage source for establishing the operational level of a multiple output current logic driver transistor. As the reference voltage source, the forward base-emitter voltage Vbe of a s... | 06/23/1987 |
| 4672579 | MTL storage cell with inherent output multiplex capability Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structu... | 06/09/1987 |
