Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 8058907 | Logic circuits, inverter devices and methods of operating the same An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first ter... | 11/15/2011 |
| 7893723 | Minimizing leakage in logic designs Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logi... | 02/22/2011 |
| 7888972 | Logic circuits, inverter devices and methods of operating the same An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first ter... | 02/15/2011 |
| 7667499 | MuGFET circuit for increasing output resistance In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a lo... | 02/23/2010 |
| 7528631 | Logic gate, scan driver and organic light emitting diode display using the same A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a ... | 05/05/2009 |
| 7436212 | Interface circuit power reduction Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit... | 10/14/2008 |
| 7420388 | Power gating techniques able to have data retention and variability immunity properties A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic... | 09/02/2008 |
| 7417469 | Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. ... | 08/26/2008 |
| 7397271 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal t... | 07/08/2008 |
| 7394294 | Complementary pass-transistor logic circuit and semiconductor device A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input n... | 07/01/2008 |
| 7382162 | High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required ... | 06/03/2008 |
| 7378876 | Complementary output inverter A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output ... | 05/27/2008 |
| 7375547 | Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit... | 05/20/2008 |
| 7372303 | Semiconductor integrated circuit A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and ... | 05/13/2008 |
| 7365576 | Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-... | 04/29/2008 |
| 7355445 | Digital circuit with smaller amplitude of input signal voltage than amplitude of power source voltage of the digital circuit In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally.... | 04/08/2008 |
| 7336104 | Multiple-output transistor logic circuit A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transis... | 02/26/2008 |
| 7336102 | Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu... | 02/26/2008 |
| 7334198 | Software controlled transistor body bias Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasin... | 02/19/2008 |
| 7317345 | Anti-gate leakage programmable capacitor An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node... | 01/08/2008 |
| 7310008 | Configurable delay chain with stacked inverter delay elements A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of sta... | 12/18/2007 |
| 7307457 | Apparatus for implementing dynamic data path with interlocked keeper and restore devices A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled ... | 12/11/2007 |
| 7304508 | Method and apparatus for fast flip-flop Embodiments related to fast flip-flops are disclosed. ... | 12/04/2007 |
| 7304876 | Compare circuit for a content addressable memory cell A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportion... | 12/04/2007 |
| 7301315 | Power supplying method and apparatus including buffer circuit to control operation of output driver A power supply circuit includes an output driver transistor, a reference voltage generator circuit, an output voltage detector circuit, an amplifier circuit, and a buffer circuit. The output driver transistor outputs a current in accordance with a first control sign... | 11/27/2007 |
| 7301850 | Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected one of a plurality of CAM arrays to the plurality of global word lin... | 11/27/2007 |
| 7298176 | Dual-gate dynamic logic circuit with pre-charge keeper A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device i... | 11/20/2007 |
| 7292064 | Minimizing timing skew among chip level outputs for registered output signals A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output c... | 11/06/2007 |
| 7292061 | Semiconductor integrated circuit having current leakage reduction scheme A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The ... | 11/06/2007 |
| 7288968 | Circuit element A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1,... | 10/30/2007 |
| 7282960 | Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage... | 10/16/2007 |
| 7279927 | Integrated circuit with multiple power domains An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source servi... | 10/09/2007 |
| 7274209 | Low voltage to high voltage signal level translator with improved performance A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third t... | 09/25/2007 |
| 7271615 | Integrated circuits with reduced leakage current In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Simil... | 09/18/2007 |
| 7263563 | Multi-bus driver apparatus and method for driving a plurality of buses A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of th... | 08/28/2007 |
| 7262631 | Method and apparatus for controlling a voltage level A voltage level control device operable to control a voltage level supplied from a first voltage level source to circuitry, said circuitry being arranged between said first voltage level source and a second voltage level source, said first and second voltage level s... | 08/28/2007 |
| 7256620 | Selector circuit and semiconductor device A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input s... | 08/14/2007 |
| 7236001 | Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei... | 06/26/2007 |
| 7230455 | Logic circuits utilizing gated diode sensing A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode an... | 06/12/2007 |
| 7227383 | Low leakage and data retention circuitry An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is ... | 06/05/2007 |
