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| Number | Title | Issue Date |
| 7317334 | Voltage translator circuit and semiconductor memory device A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 ... | 01/08/2008 |
| 7265574 | Fail-safe method and circuit A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch le... | 09/04/2007 |
| 7138835 | Method and apparatus for an equalizing buffer A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is est... | 11/21/2006 |
| 7129767 | Methods of manufacture for a low control voltage switch A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected bet... | 10/31/2006 |
| 7123045 | Semiconductor integrated circuit device When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released. ... | 10/17/2006 |
| 7106093 | Semiconductor device A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set... | 09/12/2006 |
| 7095246 | Variable impedance output buffer An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), ... | 08/22/2006 |
| 7020450 | Active inductors using bipolar silicon transistors An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and betw... | 03/28/2006 |
| 6542007 | Inverter circuit An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.... | 04/01/2003 |
| 6239623 | Direct coupling field effect transistor logic (DCFL) circuit In a DCFL circuit, a high-speed operation is conducted in a stable state regardless of its load capacitance. The circuit includes a buffer circuit. Added to the buffer circuit is a pull-up circuit conducting a pull-up operation for a predetermined period ... | 05/29/2001 |
| 6051993 | Level shift circuit compensating for circuit element characteristic variations A level shift circuit which drops the output voltage of a prior stage circuit to an input voltage level required at a next stage circuit includes a source follower enhancement-type FET, a gate of which is connected as an input terminal, a drain of which i... | 04/18/2000 |
| 5909128 | FETs logic circuit A semiconductor integrated circuit having a field effect transistor formed on a compound semiconductor is disclosed, that comprises a first power supply, a second power supply for supplying a voltage lower than a voltage that the first power supplies, and... | 06/01/1999 |
| 5822235 | Rectifying transfer gate circuit A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the so... | 10/13/1998 |
| 5726591 | MESFET logic device with clamped output drive capacity and low power A logic gate circuit includes a logic gate stage to which an input signal is supplied, for outputting a signal depending on a state of the input signal, an output driver stage having an enhancement-type transistor for pull-up and a pull-down circuit, the ... | 03/10/1998 |
| 5696453 | GaAs logic circuit with temperature compensation circuitry The invention provides a logic circuit including (a) a load element having ends one of which is electrically connected to a first terminal of a voltage source, and the other to an output terminal, (b) a first enhancement mode FET including a drain electro... | 12/09/1997 |
| 5592108 | Interface circuit adapted for connection to following circuit using metal-semiconductor type transistor An interface circuit includes an input current limiting circuit for limiting a current of an input signal fed from a preceding circuit, thereby outputting the current-limited signal to a following circuit which is constituted using a MES type transistor. ... | 01/07/1997 |
| 5451890 | Gallium arsenide source follower FET logic family with diodes for preventing leakage currents The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connecte... | 09/19/1995 |
| 5451888 | Direct coupled FET logic translator circuit A semiconductor circuit for converting high and low input signals at first and second voltage levels to high and low output signals at third and fourth voltage levels includes first, second, and third power supply lines receiving driving voltages at first... | 09/19/1995 |
| 5336949 | Logic circuit with enhancement type FET and Schottky gate A logic circuit comprising an inverter which includes a load element connected at its one end to a high-potential power supply, an enhancement type N-channel field-effect transistor having a Schottky gate, the transistor being connected at its drain to an... | 08/09/1994 |
| 5087836 | Electronic circuit including a parallel combination of an E-FET and a D-FET A class AB amplifier comprises a pull-up structure of an E-FET and D-FET connected in parallel and a pull-down structure of an E-FET and D-FET connected in parallel. Use of the E-FETs allows a high peak current to be achieved without increasing the quiesc... | 02/11/1992 |
| 5077494 | Wide temperature range MESFET logic circuit A first Schottky diode is connected between the source of a first enhancement JFET and a low voltage line. The drain of the first enhancement JFET is connected through a first active load current source to a high voltage line, and also through a second Sc... | 12/31/1991 |
| 5027007 | FFL/QFL FET logic circuits An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this in... | 06/25/1991 |
| 5021686 | Logic circuit A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and... | 06/04/1991 |
| 4958089 | High output drive FET buffer for providing high initial current to a subsequent stage An output buffer provides high current at an output for only a brief period, while after this brief period the output buffer only supplies a limited amount of current to the subsequent stage. One embodiment of this inventive output buffer utilizes the inh... | 09/18/1990 |
| 4954730 | Complementary FET circuit having merged enhancement/depletion FET output A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the compl... | 09/04/1990 |
| 4939390 | Current-steering FET logic circuit An integrated circuit, having applicability to GaAs circuitry, is disclosed for performing a current steering logic function. The integrated circuit comprises a switching circuit, a high impedance tail current source, and a pair of low impedances respectf... | 07/03/1990 |
| 4937474 | Low power, high noise margin logic gates employing enhancement mode switching FETs A low power, high noise margin logic gate comprises: an input terminal, an output terminal, and first and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal, a source and a drain; a load device... | 06/26/1990 |
| 4935647 | Group III - V semiconductor devices with improved switching speeds To decrease the time required to charge parasitic capacitances, and to thereby increase the maximum permissible switching frequency to which a logic circuit can respond, a GaAs device is disclosed having a current-injecting circuit that generates an initi... | 06/19/1990 |
| 4931669 | High speed logic circuit having output feedback In an NOR logic circuit employing an MES (Metal Semiconductor Junction) field effect transistors, an MES field effect transistor 2 for driving an output stage operates in response to an input signal applied to an input terminal 101 or 102 to output an out... | 06/05/1990 |
| 4931670 | TTL and CMOS logic compatible GAAS logic family A novel logic gate, using Gallium-Arsenide technology, that is compatible with TTL or CMOS logic. This logic gate operates off a single voltage supply (e.g. 5 volts) and implements complex logic functions within a single logic gate, such as "AND-OR-INVERT... | 06/05/1990 |
| 4918336 | Capacitor coupled push pull logic circuit This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.... | 04/17/1990 |
| 4912745 | Logic circuit connecting input and output signal lines This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handl... | 03/27/1990 |
| 4885480 | Source follower field-effect logic gate (SFFL) suitable for III-V technologies A high speed logic circuit having extremely low propagation delays, suitable for implementation in III-V technology. A logic stage provides the desired logic function by combining a predetermined number of input FETs. The drains of the input FETs couple t... | 12/05/1989 |
| 4877976 | Cascade FET logic circuits A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field... | 10/31/1989 |
| 4853561 | Family of noise-immune logic gates and memory cells A new family of memory cells and digital-logic gates use an enhancement-mode driver, a voltage-level shifter, and a current regulator to provide improved noise margins and large logic swings. The voltage-level shifter and the current regulator are connect... | 08/01/1989 |
| 4808851 | ECL-compatible semiconductor device having a prediffused gate array A semiconductor device includes a prediffused array of elementary gates which constitute an integrated circuit (designated as a "custom made circuit") realized on gallium arsenide. The elementary gates which constitute the elements of the prediffused arra... | 02/28/1989 |
| 4798979 | Schottky diode logic for E-mode FET/D-mode FET VLSI circuits A digital logic circuit using Schottky diodes as the nonlinear logic element, a single power supply and an E-mode MESFET as an inverter in the open drain configuration. Temperature compensation of the threshold voltage of the E-mode FET is provided. The c... | 01/17/1989 |
| 4798978 | GAAS FET logic having increased noise margin A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.... | 01/17/1989 |
| 4771189 | FET gate current limiter circuit A GaAs logic circuit including a current control FET that provides high current for switching an output FET, but limits the forward biasing of the output FET at the end of a transition to input logic 1 by controlling the steady state value of current to a... | 09/13/1988 |
| 4725743 | Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single ... | 02/16/1988 |
