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| Number | Title | Issue Date |
| 7994825 | Serial output circuit, semiconductor device, and serial transmission method In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial... | 08/09/2011 |
| 7872503 | Combinatorial logic circuit It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply curren... | 01/18/2011 |
| 7812643 | Implementing CML multiplexer load balancing A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first dif... | 10/12/2010 |
| 7808281 | Differential common mode logic driver with switching control circuit A differential CML driver includes an output stage, a control circuit and a reference circuit. The output stage includes a first loading component, a second loading component, a bias component, a first metal-oxide-semiconductor (MOS) transistor and a second MOS tran... | 10/05/2010 |
| 7724037 | Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switc... | 05/25/2010 |
| 7710159 | Muller-c element The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing ... | 05/04/2010 |
| 7656198 | Method and apparatus for providing a combination differential driver In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal... | 02/02/2010 |
| 7605613 | Bulk input current switch logic circuit A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier gen... | 10/20/2009 |
| 7605614 | Bulk input current switch logic circuit A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier gen... | 10/20/2009 |
| 7564268 | Low power logic output buffer A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes fir... | 07/21/2009 |
| 7560957 | High-speed CML circuit design A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor cou... | 07/14/2009 |
| 7532037 | Enhanced CML driver circuit for “quiet-driver” measurement enablement A method for enhancing a CML driver circuit to allow efficient, and accurate measurement of the magnitude of the voltage domain noise present near a CML driver in an integrated circuit. The disclosed method for enhancing a CML driver circuit to enable quiet driver m... | 05/12/2009 |
| 7495477 | Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switc... | 02/24/2009 |
| 7463068 | Apparatus and method for over-voltage, under-voltage and over-current stress protection for transceiver input and output circuitry A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An ou... | 12/09/2008 |
| 7439773 | Integrated circuit communication techniques An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which d... | 10/21/2008 |
| 7432741 | Controllable pre-distortion for transmitter circuitry on programmable logic device integrated circuits Transmitter driver circuitry includes multiple output driver stages, each of which receives a respective differently-phased version of an output signal for application to an output node of the circuitry. Each stage includes a primary current source. The circuitry al... | 10/07/2008 |
| 7429874 | Replica bias circuit Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors ... | 09/30/2008 |
| 7425847 | Input buffer with optimal biasing and method thereof A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averag... | 09/16/2008 |
| 7408385 | Receiver circuit, differential signal receiver circuit, interface circuit, and electronic instrument A receiver circuit, which is connected with a partner transmitter circuit through a signal line and receives a signal based on current which flows through the signal line, includes a current/voltage conversion circuit which converts the current which flows through t... | 08/05/2008 |
| 7405600 | Current mode logic-CMOS converter A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the volta... | 07/29/2008 |
| 7400169 | Inductor-tuned buffer circuit with improved modeling and design According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further inclu... | 07/15/2008 |
| 7400173 | Differential receiver with wide input common mode range and low duty cycle distortion A transmission system, circuit and method are provided herein for converting differential signals into low duty cycle distortion, single-ended signals that are insensitive to variations in PVT and input common mode voltage. In one embodiment, the signal translation ... | 07/15/2008 |
| 7400170 | Differential current-mode driver with high common-mode range and controlled edge rates A differential current-mode driver that meets the IEEE 1394 standard employs a wide output range in common-mode voltage, minimizes timing skew over this wide range, and has well-controlled rise/fall times in the edge rates of the digital signals transmitted, within ... | 07/15/2008 |
| 7397270 | Dynamically-adjustable differential output drivers Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuit... | 07/08/2008 |
| 7397283 | Digital A/V transmission PHY signaling format conversion, multiplexing, and de-multiplexing A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal fo... | 07/08/2008 |
| 7394283 | CML to CMOS signal converter A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode referenc... | 07/01/2008 |
| 7388406 | CML circuit devices having improved headroom A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a fir... | 06/17/2008 |
| 7385426 | Low current offset integrator with signal independent low input capacitance buffer circuit A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transcon... | 06/10/2008 |
| 7368955 | Current-balanced logic circuit In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifi... | 05/06/2008 |
| 7366484 | Systems and methods for adjusting the bias level of a mixer in a transmitter A mixer having dynamic biasing, comprises a mixer configured to receive a local oscillator (LO) reference signal and a radio frequency (RF) data signal, and a bias control circuit configured to reduce bias current from the mixer under a low power condition. ... | 04/29/2008 |
| 7362140 | Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic ... | 04/22/2008 |
| 7358873 | LVDS and TMDS dualfunction device A LVDS and TMDS dualfunction transmitter for both LVDS and TMDS output channels is disclosed, including an encoder and a serializer. The encoder encodes twenty eight bits of LVDS signals to thirty bits of TMDS signals. The serializer includes four serializer channel... | 04/15/2008 |
| 7355451 | Common-mode shifting circuit for CML buffers A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tendi... | 04/08/2008 |
| 7352207 | Output driver with common mode feedback A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differen... | 04/01/2008 |
| 7342420 | Low power output driver A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first l... | 03/11/2008 |
| 7342423 | Circuit and method for calculating a logical combination of two input operands A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a... | 03/11/2008 |
| 7336104 | Multiple-output transistor logic circuit A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transis... | 02/26/2008 |
| 7330056 | Low power CMOS LVDS driver A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching st... | 02/12/2008 |
| 7330709 | Receiver circuit using nanotube-based switches and logic Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. ... | 02/12/2008 |
| 7327184 | Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input tra... | 02/05/2008 |
