Class 326/113 - Pass transistor logic or transmission gate logic

Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter wherein a field-effect transistor performs
No. of patents: 344
Last issue date: 04/24/2012

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Number	Title	Issue Date
8164361	Low power complementary logic latch and RF divider A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the loc...	04/24/2012
8102190	Power efficient multiplexer A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for invert...	01/24/2012
7924060	Output circuit of semiconductor device An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configu...	04/12/2011
7812642	Pass gate with improved latchup immunity An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected t...	10/12/2010
7795923	Logic circuit A logic circuit includes first, second, third and fourth transistors. The first transistor is a first type, and has a gate terminal for receiving a control signal representative of one of NAND and NOR operations of at least first and second signals, a first terminal...	09/14/2010
7782092	Cascaded pass-gate test circuit with interposed split-output drive devices A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring osci...	08/24/2010
7768317	Radiation-tolerant flash-based FPGA memory cells A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired i...	08/03/2010
7683674	T-switch buffer, in particular for FPGA architectures An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-...	03/23/2010
7633316	Transmission gate multiplexer A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission...	12/15/2009
7498846	Power efficient multiplexer A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for invert...	03/03/2009
7466165	Transmission gate multiplexer A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission...	12/16/2008
7466164	Method and apparatus for a configurable low power high fan-in multiplexer A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select s...	12/16/2008
7463067	Switch block for FPGA architectures A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power. ...	12/09/2008
7439774	Multiplexing circuit for decreasing output delay time of output signal Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, a...	10/21/2008
7436220	Partially gated mux-latch keeper Embodiments related to multiplexer latches (mux-latches) are presented herein. ...	10/14/2008
7429879	Clock receiver circuit device, in particular for semi-conductor components A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver circuit device includes a first input adapted to be connected with a firs...	09/30/2008
7429872	Logic circuit combining exclusive OR gate and exclusive NOR gate A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connec...	09/30/2008
7423448	Radiation hardened logic circuit A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitr...	09/09/2008
7417454	Low-swing interconnections for field programmable gate arrays An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shift...	08/26/2008
7417468	Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style...	08/26/2008
7411424	Programmable logic function generator using non-volatile programmable memory switches Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus em...	08/12/2008
7411412	Semiconductor integrated circuit A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modu...	08/12/2008
7411423	Logic activation circuit Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of ...	08/12/2008
7394294	Complementary pass-transistor logic circuit and semiconductor device A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input n...	07/01/2008
7365574	General purpose delay logic A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising a...	04/29/2008
7365576	Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-...	04/29/2008
7362140	Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic ...	04/22/2008
7358768	XOR-based conditional keeper and an architecture implementing its application to match lines The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooper...	04/15/2008
7358769	XOR circuit An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output. ...	04/15/2008
7355435	On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs...	04/08/2008
7355881	Memory array with global bitline domino read/write scheme A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells i...	04/08/2008
7352275	Device for comparing two words of n bits each The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=...	04/01/2008
7352211	Signal history controlled slew-rate transmission method and bus interface transmitter A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis...	04/01/2008
7350177	Configurable logic and memory devices A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB fu...	03/25/2008
7345511	Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors fo...	03/18/2008
7342415	Configurable IC with interconnect circuits that also perform storage operations Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circ...	03/11/2008
7336104	Multiple-output transistor logic circuit A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transis...	02/26/2008
7328423	Method for evaluating logic functions by logic circuits having optimized number of and/or switches A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present inve...	02/05/2008
7327169	Clocked inverter, NAND, NOR and shift register A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the pre...	02/05/2008
7323910	Circuit arrangement and method for producing a dual-rail signal Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via one of the switches to a signal processing apparatus foot point, which...	01/29/2008

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Class 326/113 - Pass transistor logic or transmission gate logic