Class 326/112 - Field-effect transistor (e.g., JFET, etc.)

Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter wherein the logic circuit includes a unipolar
No. of patents: 382
Last issue date: 04/17/2012

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Number	Title	Issue Date
8159271	Scan driver A scan driver includes a voltage setting circuit, a counter circuit, a logic circuit, a dynamic decoder, N level shift circuits and N output stage circuits, wherein N is a natural number. The voltage setting circuit sets N voltage signals to a first level. The count...	04/17/2012
7999575	Semiconductor integrated circuit device A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type...	08/16/2011
7994824	Logic gate with a reduced number of switches, especially for applications in integrated circuits Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed poten...	08/09/2011
7688117	N channel JFET based digital logic gate structure A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct curr...	03/30/2010
7663408	Scannable dynamic circuit latch A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a f...	02/16/2010
7635992	Configurable tapered delay chain with multiple sizes of delay elements A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter...	12/22/2009
7633315	Semiconductor integrated circuit device An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the pre...	12/15/2009
7592840	Domino circuit with disable feature Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage. ...	09/22/2009
7535261	Logic circuit A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and sec...	05/19/2009
7474125	Method of producing and operating a low power junction field effect transistor A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a...	01/06/2009
7436212	Interface circuit power reduction Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit...	10/14/2008
7436215	Transmitter In some embodiments, a transmitter includes a first circuit coupled to an input port of the transmitter, and a second circuit coupled to the first circuit and to an output port of the transmitter, wherein the first circuit is sized with respect to the second circuit...	10/14/2008
7429880	Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS...	09/30/2008
7428160	Nonvolatile programmable logic circuit A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPG...	09/23/2008
7420388	Power gating techniques able to have data retention and variability immunity properties A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic...	09/02/2008
7417469	Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. ...	08/26/2008
7417468	Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style...	08/26/2008
7403038	Semiconductor device and display device A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to...	07/22/2008
7397271	Semiconductor integrated circuit device A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal t...	07/08/2008
7394294	Complementary pass-transistor logic circuit and semiconductor device A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input n...	07/01/2008
7394297	Logic gate with reduced sub-threshold leak current The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first ...	07/01/2008
7388406	CML circuit devices having improved headroom A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a fir...	06/17/2008
7385441	Level shifter with reduced power consumption A buffer circuit has a first transistor and a second transistor in a cascode, and a buffer switch coupled from an output of the buffer to a gate of the second transistor. The buffer circuit is bootstrapped by a bootstrap capacitor, a diode circuit, and a bootstrap s...	06/10/2008
7382162	High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required ...	06/03/2008
7375547	Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit...	05/20/2008
7365576	Binary digital latches not using only NAND or NOR circuits A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-...	04/29/2008
7363595	Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation. The method includes a signal termination device coupled to a driver output pad. In one embodiment, driver includes a pull-up circuit having at least on...	04/22/2008
7345511	Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors fo...	03/18/2008
7342423	Circuit and method for calculating a logical combination of two input operands A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a...	03/11/2008
7342846	Address decoding systems and methods Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signa...	03/11/2008
7336104	Multiple-output transistor logic circuit A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transis...	02/26/2008
7336102	Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu...	02/26/2008
7336105	Dual gate transistor keeper dynamic logic A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its inp...	02/26/2008
7312640	Semiconductor integrated circuit device having power reduction mechanism A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a curren...	12/25/2007
7307457	Apparatus for implementing dynamic data path with interlocked keeper and restore devices A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled ...	12/11/2007
7301371	Transmitter of a semiconductor device Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a con...	11/27/2007
7298171	Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than trad...	11/20/2007
7295042	Buffer A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull ope...	11/13/2007
7294935	Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle...	11/13/2007
7292064	Minimizing timing skew among chip level outputs for registered output signals A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output c...	11/06/2007

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Class 326/112 - Field-effect transistor (e.g., JFET, etc.)